共用回授機制的低成本機率式抗雜訊電路設計與實現

Translated title of the contribution: Design and Implementation of Cost-Effective Probabilistic-Based Noise-Tolerant VLSI Circuits by Using Common Valid Minterm Feedback Loops

沈業智

Research output: Types of Thesis › Master's thesis

Translated title of the contributionDesign and Implementation of Cost-Effective Probabilistic-Based Noise-Tolerant VLSI Circuits by Using Common Valid Minterm Feedback Loops
Original languageChinese (Traditional)
Supervisors/Advisors
  • Wey, I-Chyn, Supervisor
StatePublished - 2010
Externally publishedYes

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