| Translated title of the contribution | Spur reduction in PLL by phase error calibration |
|---|---|
| Original language | Chinese (Traditional) |
| Supervisors/Advisors |
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| State | Published - 2012 |
| Externally published | Yes |
具相位誤差校正與抑制突波之鎖相迴路
- 鄭世宏
Research output: Types of Thesis › Master's thesis