Abstract
This work presents a modified bit-parallel systolic architecture for computing C+AB, AB, C+AB2 or AB2 over a class of GF(2m) based on the irreducible all one polynomial (AOP) or the irreducible equally spaced polynomial (ESP), where A, B and C are elements of GF(2m). If elements over GF(2m) are represented by extended forms, then these elements have two important properties: first, the polynomial of the elements is cyclic with modulo xm+1+1, and second, some fixed zero terms of the product of two elements can be ignored in the polynomials. Then, with these properties, ringed low-complexity bit-parallel systolic multipliers are presented. The ringed bit-parallel systolic multiplier over the class of GF(2m) requires few gates and no global connections. Accordingly, the new multiplier has a low complexity and few input pins. This ringed configuration can be easily implemented by taking advantage of three-dimensional routing in VLSI systems. The architecture of the multiplier was designed over GF(24), based on the irreducible AOP, or over GF(26), based on the irreducible ESP as examples, respectively. Notably, the field GF(24) or GF(26) is used to illustrate the structures and operations of the two new multipliers presented in this paper, however, the extension of these structures to a general case of GF(2m) is straightforward.
Translated title of the contribution | A modified bit-parallel systolic architecture for computing C+AB, AB, C+AB2 or AB2 over a class of GF(2m) |
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Original language | Chinese (Traditional) |
Patent number | I267778 |
IPC | G06F-007/44(2006.01);G06F-007/50(2006.01) |
State | Published - 01 12 2006 |
Bibliographical note
公開公告號: I267778Announcement ID: I267778