基於VT Balancer架構的近臨界電壓加法器電路設計

Translated title of the contribution: VT Balancer Architecture for Near Threshold Voltage Full Adder Design

魏光科

Research output: Types of Thesis › Master's thesis

Translated title of the contributionVT Balancer Architecture for Near Threshold Voltage Full Adder Design
Original languageChinese (Traditional)
Supervisors/Advisors
  • Wey, I-Chyn, Supervisor
StatePublished - 2015
Externally publishedYes

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