| Translated title of the contribution | Analysis and design of 0.3V µW power phase-locked loop with variation suppression for IoT applications |
|---|---|
| Original language | Chinese (Traditional) |
| Supervisors/Advisors |
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| State | Published - 2025 |
| Externally published | Yes |
應用於物聯網的0.3伏特微瓦級具變異作用抑制鎖相迴路分析與設計
- 伍冠維
Research output: Types of Thesis › Master's thesis