搜尋積體電路設計中具有靜電放電威脅路徑之方法

A method for searching ESD threatening path in an integrated circuit design is provided. In a general IC design flow, through input netlist, leads and paths among leads are diagnosed to check the possibility of high current level electrostatic current that is generated by electrostatic discharge (ESD). The invented method can decide the design consideration of ESD protection circuits in the initial stage of circuit design not adding such circuit at every lead, so as the circuit design needed time and resource are reduced.