次/近臨界電壓之位元序列行並列單指令多資料加速器設計與實現

Translated title of the contribution: Sub/Near-Threshold Voltage Bit-Serial Column-Parallel SIMD Accelerator Design and Implementation

吳秉宸

Research output: Types of ThesisMaster's thesis

Translated title of the contributionSub/Near-Threshold Voltage Bit-Serial Column-Parallel SIMD Accelerator Design and Implementation
Original languageChinese (Traditional)
Supervisors/Advisors
  • Wey, I-Chyn, Supervisor
StatePublished - 2015
Externally publishedYes

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