超大型數位積體電路之同步電路時脈偏移量排程與最佳化設計

Translated title of the contribution: Clock Skew Scheduling and Optimization for Large-Scale Digital Synchronous Circuits

張兆凱

Research output: Types of Thesis › Master's thesis

Translated title of the contribution	Clock Skew Scheduling and Optimization for Large-Scale Digital Synchronous Circuits
Original language	Chinese (Traditional)
Supervisors/Advisors	Chu, Chia-Chi, Supervisor
State	Published - 2005
Externally published	Yes

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