閘控式主運算電路搭配高精準度固定寬度冗餘電路之低功率演算法層級抗雜訊電路設計

Translated title of the contribution: Low-Power Algorithmic Noise-Tolerant Circuit Design Based on Gated Main Arithmetic Block and Precise Fixed-Width Reduced Precision Redundancy

陳羿廷

Research output: Types of ThesisMaster's thesis

Translated title of the contributionLow-Power Algorithmic Noise-Tolerant Circuit Design Based on Gated Main Arithmetic Block and Precise Fixed-Width Reduced Precision Redundancy
Original languageChinese (Traditional)
Supervisors/Advisors
  • Wey, I-Chyn, Supervisor
StatePublished - 2011
Externally publishedYes

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