高速超大型積體電路中金屬連線的延遲時間與串音雜訊之模擬

Translated title of the contribution: Delay Time and Crosstalk Simulation of Interconnections for High Speed VLSI

林昇平

Research output: Types of Thesis › Master's thesis

Translated title of the contributionDelay Time and Crosstalk Simulation of Interconnections for High Speed VLSI
Original languageChinese (Traditional)
Supervisors/Advisors
  • Lee, J. Yen, Supervisor
StatePublished - 2000
Externally publishedYes

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