1V 10-bit successive approximation ADC for low power biomedical applications

Hwang Cherng Chow; Yi Hung Chen

doi:10.1109/ECCTD.2007.4529570

1V 10-bit successive approximation ADC for low power biomedical applications

Hwang Cherng Chow, Yi Hung Chen

Department of Electronic Engineering

Chang Gung University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

12 Scopus citations

Abstract

A low power 1V 10-bit successive approximation analog-to-digital converter (SA-ADC) is presented for biomedical applications. In the DAC capacitor arrays of this SA-ADC a charge-recycling method for switching the capacitors is used. Besides, a 1V rail-to-rail input comparator with both current driven bulk technique and offset cancellation is proposed. The complete 1V ADC implemented in TSMC 0.18um CMOS process has a signal-to-noise ratio of 58.5dB and its effective number of bits is 9.4 based on post-layout simulations. The entire ADC power consumption is 32.6uW for normal signals and 29.5uW for ECG applications.

Original language	English
Title of host publication	European Conference on Circuit Theory and Design 2007, ECCTD 2007
Publisher	IEEE Computer Society
Pages	196-199
Number of pages	4
ISBN (Print)	1424413427, 9781424413423
DOIs	https://doi.org/10.1109/ECCTD.2007.4529570
State	Published - 2007
Event	European Conference on Circuit Theory and Design 2007, ECCTD 2007 - Seville, Spain Duration: 26 08 2007 → 30 08 2007

Publication series

Name	European Conference on Circuit Theory and Design 2007, ECCTD 2007

Conference

Conference	European Conference on Circuit Theory and Design 2007, ECCTD 2007
Country/Territory	Spain
City	Seville
Period	26/08/07 → 30/08/07

Access to Document

10.1109/ECCTD.2007.4529570

Cite this

@inproceedings{b437a325d20d4acf8e6ef385cb293484,

title = "1V 10-bit successive approximation ADC for low power biomedical applications",

abstract = "A low power 1V 10-bit successive approximation analog-to-digital converter (SA-ADC) is presented for biomedical applications. In the DAC capacitor arrays of this SA-ADC a charge-recycling method for switching the capacitors is used. Besides, a 1V rail-to-rail input comparator with both current driven bulk technique and offset cancellation is proposed. The complete 1V ADC implemented in TSMC 0.18um CMOS process has a signal-to-noise ratio of 58.5dB and its effective number of bits is 9.4 based on post-layout simulations. The entire ADC power consumption is 32.6uW for normal signals and 29.5uW for ECG applications.",

author = "Chow, \{Hwang Cherng\} and Chen, \{Yi Hung\}",

year = "2007",

doi = "10.1109/ECCTD.2007.4529570",

language = "英语",

isbn = "1424413427",

series = "European Conference on Circuit Theory and Design 2007, ECCTD 2007",

publisher = "IEEE Computer Society",

pages = "196--199",

booktitle = "European Conference on Circuit Theory and Design 2007, ECCTD 2007",

address = "美国",

note = "European Conference on Circuit Theory and Design 2007, ECCTD 2007 ; Conference date: 26-08-2007 Through 30-08-2007",

}

Chow, HC & Chen, YH 2007, 1V 10-bit successive approximation ADC for low power biomedical applications. in European Conference on Circuit Theory and Design 2007, ECCTD 2007., 4529570, European Conference on Circuit Theory and Design 2007, ECCTD 2007, IEEE Computer Society, pp. 196-199, European Conference on Circuit Theory and Design 2007, ECCTD 2007, Seville, Spain, 26/08/07. https://doi.org/10.1109/ECCTD.2007.4529570

1V 10-bit successive approximation ADC for low power biomedical applications. / Chow, Hwang Cherng; Chen, Yi Hung.
European Conference on Circuit Theory and Design 2007, ECCTD 2007. IEEE Computer Society, 2007. p. 196-199 4529570 (European Conference on Circuit Theory and Design 2007, ECCTD 2007).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

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AU - Chen, Yi Hung

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N2 - A low power 1V 10-bit successive approximation analog-to-digital converter (SA-ADC) is presented for biomedical applications. In the DAC capacitor arrays of this SA-ADC a charge-recycling method for switching the capacitors is used. Besides, a 1V rail-to-rail input comparator with both current driven bulk technique and offset cancellation is proposed. The complete 1V ADC implemented in TSMC 0.18um CMOS process has a signal-to-noise ratio of 58.5dB and its effective number of bits is 9.4 based on post-layout simulations. The entire ADC power consumption is 32.6uW for normal signals and 29.5uW for ECG applications.

AB - A low power 1V 10-bit successive approximation analog-to-digital converter (SA-ADC) is presented for biomedical applications. In the DAC capacitor arrays of this SA-ADC a charge-recycling method for switching the capacitors is used. Besides, a 1V rail-to-rail input comparator with both current driven bulk technique and offset cancellation is proposed. The complete 1V ADC implemented in TSMC 0.18um CMOS process has a signal-to-noise ratio of 58.5dB and its effective number of bits is 9.4 based on post-layout simulations. The entire ADC power consumption is 32.6uW for normal signals and 29.5uW for ECG applications.

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DO - 10.1109/ECCTD.2007.4529570

M3 - 会议稿件

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SN - 9781424413423

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BT - European Conference on Circuit Theory and Design 2007, ECCTD 2007

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T2 - European Conference on Circuit Theory and Design 2007, ECCTD 2007

Y2 - 26 August 2007 through 30 August 2007

ER -

1V 10-bit successive approximation ADC for low power biomedical applications

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