3-D graphics processor unit with cost-effective rasterization using valid screen space region

In order to render 3-D graphics efficiently, rasterization techniques have been developed. Traditional clipping techniques using six-planes of view volume are complicated and not cost-effective. This paper develops a novel cost-effective strategy for primitives with regard to clipping in rasterization. Throughout the process, no expensive clipping action is required and no extra clipping-derived polygons are produced. It also presents the architecture of a 200-MHz multicore, multi-thread 3-D graphics SoC in 65nm 1P9M process with a core size of 4.97mm2 and 153.3mW for power consumption. The proposed clip-less architecture in rasterization processes the valid screen space region of each primitive in eight cycles, with a gate-count of only 20k. In addition, the throughput can achieve up to 25 M Triangles/Sec.