A 0.13μm hardware-efficient probabilistic-based noise-tolerant circuit design and implementation with 24.5dB noise-immunity improvement

I. Chyn Wey; You Gang Chen; Changhong Yu; Jie Chen; An Yeu Wu

doi:10.1109/ASSCC.2007.4425694

A 0.13μm hardware-efficient probabilistic-based noise-tolerant circuit design and implementation with 24.5dB noise-immunity improvement

I. Chyn Wey^*
, You Gang Chen
, Changhong Yu
, Jie Chen
, An Yeu Wu

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

As the size of CMOS devices is scaled down to the nanoscale level, noise interferences start to significantly affect the VLSI circuit performance. Because the noise is random and dynamic in nature, a probabilistic-based approach is more suitable to handle signal errors than the conventional deterministic circuit designs. However, probabilistic-based designs cost larger hardware area. In this paper, we design and implement a hardware-efficient probabilistic-based noise-tolerant circuit, an 8-bit Markov Random Field carry lookahead adder (MRF_CLA), in 0.13μm CMOS process technology. The measurement results show that the proposed MRF_CLA can provide 24.5dB of noise-immunity enhancement as compared with its conventional CMOS design. Moreover, the transistor count can be saved 42% as compared to the state-of-art MRF design [1].

Original language	English
Title of host publication	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
Pages	316-319
Number of pages	4
DOIs	https://doi.org/10.1109/ASSCC.2007.4425694
State	Published - 2007
Externally published	Yes
Event	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC - Jeju, Korea, Republic of Duration: 12 11 2007 → 14 11 2007

Publication series

Name	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

Conference

Conference	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
Country/Territory	Korea, Republic of
City	Jeju
Period	12/11/07 → 14/11/07

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10.1109/ASSCC.2007.4425694

Cite this

Wey, I. C., Chen, Y. G., Yu, C., Chen, J., & Wu, A. Y. (2007). A 0.13μm hardware-efficient probabilistic-based noise-tolerant circuit design and implementation with 24.5dB noise-immunity improvement. In 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC (pp. 316-319). Article 4425694 (2007 IEEE Asian Solid-State Circuits Conference, A-SSCC). https://doi.org/10.1109/ASSCC.2007.4425694

@inproceedings{349dd71aac4a4d0590bdb6c72c639aee,

title = "A 0.13μm hardware-efficient probabilistic-based noise-tolerant circuit design and implementation with 24.5dB noise-immunity improvement",

abstract = "As the size of CMOS devices is scaled down to the nanoscale level, noise interferences start to significantly affect the VLSI circuit performance. Because the noise is random and dynamic in nature, a probabilistic-based approach is more suitable to handle signal errors than the conventional deterministic circuit designs. However, probabilistic-based designs cost larger hardware area. In this paper, we design and implement a hardware-efficient probabilistic-based noise-tolerant circuit, an 8-bit Markov Random Field carry lookahead adder (MRF\_CLA), in 0.13μm CMOS process technology. The measurement results show that the proposed MRF\_CLA can provide 24.5dB of noise-immunity enhancement as compared with its conventional CMOS design. Moreover, the transistor count can be saved 42\% as compared to the state-of-art MRF design [1].",

author = "Wey, \{I. Chyn\} and Chen, \{You Gang\} and Changhong Yu and Jie Chen and Wu, \{An Yeu\}",

year = "2007",

doi = "10.1109/ASSCC.2007.4425694",

language = "英语",

isbn = "1424413605",

series = "2007 IEEE Asian Solid-State Circuits Conference, A-SSCC",

pages = "316--319",

booktitle = "2007 IEEE Asian Solid-State Circuits Conference, A-SSCC",

note = "2007 IEEE Asian Solid-State Circuits Conference, A-SSCC ; Conference date: 12-11-2007 Through 14-11-2007",

}

Wey, IC, Chen, YG, Yu, C, Chen, J & Wu, AY 2007, A 0.13μm hardware-efficient probabilistic-based noise-tolerant circuit design and implementation with 24.5dB noise-immunity improvement. in 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC., 4425694, 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC, pp. 316-319, 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC, Jeju, Korea, Republic of, 12/11/07. https://doi.org/10.1109/ASSCC.2007.4425694

A 0.13μm hardware-efficient probabilistic-based noise-tolerant circuit design and implementation with 24.5dB noise-immunity improvement. / Wey, I. Chyn; Chen, You Gang; Yu, Changhong et al.
2007 IEEE Asian Solid-State Circuits Conference, A-SSCC. 2007. p. 316-319 4425694 (2007 IEEE Asian Solid-State Circuits Conference, A-SSCC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Wey, I. Chyn

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AU - Chen, Jie

AU - Wu, An Yeu

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AB - As the size of CMOS devices is scaled down to the nanoscale level, noise interferences start to significantly affect the VLSI circuit performance. Because the noise is random and dynamic in nature, a probabilistic-based approach is more suitable to handle signal errors than the conventional deterministic circuit designs. However, probabilistic-based designs cost larger hardware area. In this paper, we design and implement a hardware-efficient probabilistic-based noise-tolerant circuit, an 8-bit Markov Random Field carry lookahead adder (MRF_CLA), in 0.13μm CMOS process technology. The measurement results show that the proposed MRF_CLA can provide 24.5dB of noise-immunity enhancement as compared with its conventional CMOS design. Moreover, the transistor count can be saved 42% as compared to the state-of-art MRF design [1].

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ER -

A 0.13μm hardware-efficient probabilistic-based noise-tolerant circuit design and implementation with 24.5dB noise-immunity improvement

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