A 0.5V high speed DRAM charge transfer sense amplifier

Hwang Cherng Chow; Chaung Lin Hsieh

doi:10.1109/MWSCAS.2007.4488787

A 0.5V high speed DRAM charge transfer sense amplifier

Hwang Cherng Chow^*, Chaung Lin Hsieh

^*Corresponding author for this work

Department of Electronic Engineering

Chang Gung University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

A new charge transfer sense amplifier scheme is proposed for high speed 0.5V DRAMs. The combination of both cross-coupled structure and boost capacitance of the proposed sense amplifier leads to the maximum voltage difference between sense nodes and 40% faster operation than prior art circuits.

Original language	English
Title of host publication	2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference Proceedings
Pages	1293-1296
Number of pages	4
DOIs	https://doi.org/10.1109/MWSCAS.2007.4488787
State	Published - 2007
Event	2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference - Montreal, QC, Canada Duration: 05 08 2007 → 08 08 2007

Publication series

Name	Midwest Symposium on Circuits and Systems
ISSN (Print)	1548-3746

Conference

Conference	2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference
Country/Territory	Canada
City	Montreal, QC
Period	05/08/07 → 08/08/07

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10.1109/MWSCAS.2007.4488787

Cite this

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title = "A 0.5V high speed DRAM charge transfer sense amplifier",

abstract = "A new charge transfer sense amplifier scheme is proposed for high speed 0.5V DRAMs. The combination of both cross-coupled structure and boost capacitance of the proposed sense amplifier leads to the maximum voltage difference between sense nodes and 40% faster operation than prior art circuits.",

author = "Chow, {Hwang Cherng} and Hsieh, {Chaung Lin}",

year = "2007",

doi = "10.1109/MWSCAS.2007.4488787",

language = "英语",

isbn = "1424411769",

series = "Midwest Symposium on Circuits and Systems",

pages = "1293--1296",

booktitle = "2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference Proceedings",

note = "2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference ; Conference date: 05-08-2007 Through 08-08-2007",

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Chow, HC & Hsieh, CL 2007, A 0.5V high speed DRAM charge transfer sense amplifier. in 2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference Proceedings., 4488787, Midwest Symposium on Circuits and Systems, pp. 1293-1296, 2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference, Montreal, QC, Canada, 05/08/07. https://doi.org/10.1109/MWSCAS.2007.4488787

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T1 - A 0.5V high speed DRAM charge transfer sense amplifier

AU - Chow, Hwang Cherng

AU - Hsieh, Chaung Lin

PY - 2007

Y1 - 2007

N2 - A new charge transfer sense amplifier scheme is proposed for high speed 0.5V DRAMs. The combination of both cross-coupled structure and boost capacitance of the proposed sense amplifier leads to the maximum voltage difference between sense nodes and 40% faster operation than prior art circuits.

AB - A new charge transfer sense amplifier scheme is proposed for high speed 0.5V DRAMs. The combination of both cross-coupled structure and boost capacitance of the proposed sense amplifier leads to the maximum voltage difference between sense nodes and 40% faster operation than prior art circuits.

UR - http://www.scopus.com/inward/record.url?scp=51449096203&partnerID=8YFLogxK

U2 - 10.1109/MWSCAS.2007.4488787

DO - 10.1109/MWSCAS.2007.4488787

M3 - 会议稿件

AN - SCOPUS:51449096203

SN - 1424411769

SN - 9781424411764

T3 - Midwest Symposium on Circuits and Systems

SP - 1293

EP - 1296

BT - 2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference Proceedings

T2 - 2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference

Y2 - 5 August 2007 through 8 August 2007

ER -

A 0.5V high speed DRAM charge transfer sense amplifier

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