A 10-bit area-efficient SAR ADC with re-usable capacitive array

Chung Yi Li; Chih Wen Lu; Hao Tsun Chao; Chin Hsia

doi:10.1109/ICASID.2012.6325302

A 10-bit area-efficient SAR ADC with re-usable capacitive array

Chung Yi Li
, Chih Wen Lu^*
, Hao Tsun Chao
, Chin Hsia

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

In this paper, an area-efficient successive approximation register (SAR) analog-to-digital converter (ADC) with a dithering V_ref is proposed. It reuses the capacitive array with the reconfiguration of V_ref to V_ref ± ΔV for reducing dramatically the ADC's area. The 2n resolution is achieved by the n bit SAR-ADC. To verify the proposed scheme, the proposed SAR ADC is implemented in a TSMC 0.18 μm 1P6M CMOS process with a supply voltage of 1.8V. The simulation results show that the capacitor area is reduced by 96% compared with the conventional 10-bit SAR-ADC. The ENOB of the proposed architecture is 9.767 bit when operating at 14MS/s.

Original language	English
Title of host publication	2012 International Conference on Anti-Counterfeiting, Security and Identification, ASID 2012
DOIs	https://doi.org/10.1109/ICASID.2012.6325302
State	Published - 2012
Externally published	Yes
Event	2012 International Conference on Anti-Counterfeiting, Security and Identification, ASID 2012 - Taipei, Taiwan Duration: 24 08 2012 → 26 08 2012

Publication series

Name	Proceedings of the International Conference on Anti-Counterfeiting, Security and Identification, ASID
ISSN (Print)	2163-5048
ISSN (Electronic)	2163-5056

Conference

Conference	2012 International Conference on Anti-Counterfeiting, Security and Identification, ASID 2012
Country/Territory	Taiwan
City	Taipei
Period	24/08/12 → 26/08/12

Access to Document

10.1109/ICASID.2012.6325302

Cite this

Li, C. Y., Lu, C. W., Chao, H. T., & Hsia, C. (2012). A 10-bit area-efficient SAR ADC with re-usable capacitive array. In 2012 International Conference on Anti-Counterfeiting, Security and Identification, ASID 2012 Article 6325302 (Proceedings of the International Conference on Anti-Counterfeiting, Security and Identification, ASID). https://doi.org/10.1109/ICASID.2012.6325302

@inproceedings{ac9019b9323f43c4820840339cde0e62,

title = "A 10-bit area-efficient SAR ADC with re-usable capacitive array",

abstract = "In this paper, an area-efficient successive approximation register (SAR) analog-to-digital converter (ADC) with a dithering Vref is proposed. It reuses the capacitive array with the reconfiguration of Vref to Vref ± ΔV for reducing dramatically the ADC's area. The 2n resolution is achieved by the n bit SAR-ADC. To verify the proposed scheme, the proposed SAR ADC is implemented in a TSMC 0.18 μm 1P6M CMOS process with a supply voltage of 1.8V. The simulation results show that the capacitor area is reduced by 96\% compared with the conventional 10-bit SAR-ADC. The ENOB of the proposed architecture is 9.767 bit when operating at 14MS/s.",

author = "Li, \{Chung Yi\} and Lu, \{Chih Wen\} and Chao, \{Hao Tsun\} and Chin Hsia",

year = "2012",

doi = "10.1109/ICASID.2012.6325302",

language = "英语",

isbn = "9781467321440",

series = "Proceedings of the International Conference on Anti-Counterfeiting, Security and Identification, ASID",

booktitle = "2012 International Conference on Anti-Counterfeiting, Security and Identification, ASID 2012",

note = "2012 International Conference on Anti-Counterfeiting, Security and Identification, ASID 2012 ; Conference date: 24-08-2012 Through 26-08-2012",

}

Li, CY, Lu, CW, Chao, HT & Hsia, C 2012, A 10-bit area-efficient SAR ADC with re-usable capacitive array. in 2012 International Conference on Anti-Counterfeiting, Security and Identification, ASID 2012., 6325302, Proceedings of the International Conference on Anti-Counterfeiting, Security and Identification, ASID, 2012 International Conference on Anti-Counterfeiting, Security and Identification, ASID 2012, Taipei, Taiwan, 24/08/12. https://doi.org/10.1109/ICASID.2012.6325302

A 10-bit area-efficient SAR ADC with re-usable capacitive array. / Li, Chung Yi; Lu, Chih Wen; Chao, Hao Tsun et al.
2012 International Conference on Anti-Counterfeiting, Security and Identification, ASID 2012. 2012. 6325302 (Proceedings of the International Conference on Anti-Counterfeiting, Security and Identification, ASID).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A 10-bit area-efficient SAR ADC with re-usable capacitive array

AU - Li, Chung Yi

AU - Lu, Chih Wen

AU - Chao, Hao Tsun

AU - Hsia, Chin

PY - 2012

Y1 - 2012

N2 - In this paper, an area-efficient successive approximation register (SAR) analog-to-digital converter (ADC) with a dithering Vref is proposed. It reuses the capacitive array with the reconfiguration of Vref to Vref ± ΔV for reducing dramatically the ADC's area. The 2n resolution is achieved by the n bit SAR-ADC. To verify the proposed scheme, the proposed SAR ADC is implemented in a TSMC 0.18 μm 1P6M CMOS process with a supply voltage of 1.8V. The simulation results show that the capacitor area is reduced by 96% compared with the conventional 10-bit SAR-ADC. The ENOB of the proposed architecture is 9.767 bit when operating at 14MS/s.

AB - In this paper, an area-efficient successive approximation register (SAR) analog-to-digital converter (ADC) with a dithering Vref is proposed. It reuses the capacitive array with the reconfiguration of Vref to Vref ± ΔV for reducing dramatically the ADC's area. The 2n resolution is achieved by the n bit SAR-ADC. To verify the proposed scheme, the proposed SAR ADC is implemented in a TSMC 0.18 μm 1P6M CMOS process with a supply voltage of 1.8V. The simulation results show that the capacitor area is reduced by 96% compared with the conventional 10-bit SAR-ADC. The ENOB of the proposed architecture is 9.767 bit when operating at 14MS/s.

UR - https://www.scopus.com/pages/publications/84870601440

U2 - 10.1109/ICASID.2012.6325302

DO - 10.1109/ICASID.2012.6325302

M3 - 会议稿件

AN - SCOPUS:84870601440

SN - 9781467321440

T3 - Proceedings of the International Conference on Anti-Counterfeiting, Security and Identification, ASID

BT - 2012 International Conference on Anti-Counterfeiting, Security and Identification, ASID 2012

T2 - 2012 International Conference on Anti-Counterfeiting, Security and Identification, ASID 2012

Y2 - 24 August 2012 through 26 August 2012

ER -

A 10-bit area-efficient SAR ADC with re-usable capacitive array

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this