A 24GHz low-power CMOS receiver design

  • Chen Yuan Chu*
  • , Chien Cheng Wei
  • , Hui Chen Hsu
  • , Shu Hau Feng
  • , Wu Shiung Feng
  • *Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

20 Scopus citations

Abstract

A 24GHz low-power CMOS RF receivers for indoor wireless application is developed in this paper. This paper presents a novel approach to integrate the RF front-end circuits, and realizes the manufacture of SoC (System on a Chip) design. The proposed RF IC includes a low-noise amplifier (LNA), a down-conversion mixer, a voltage-controlled oscillator (VCO) and a variable gain amplifier (VGA). For the demands of a low-power design, the LNA and VCO were designed with current-reused technology for lowering the dc power consumption, and the current-bleeding approach was adopted in mixer design for boosting its conversion gain, respectively. The proposed 24GHz CMOS RF receiver achieves the overall conversion gain of 23.4dB with noise figure of 5.4dB, and the total power consumption is only 31.65mW. Compared to the other papers published over the past few years, this paper exhibits a better potential in low-power design than other receivers applied in the same frequency band.

Original languageEnglish
Title of host publication2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
Pages980-983
Number of pages4
DOIs
StatePublished - 2008
Externally publishedYes
Event2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 - Seattle, WA, United States
Duration: 18 05 200821 05 2008

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Conference

Conference2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
Country/TerritoryUnited States
CitySeattle, WA
Period18/05/0821/05/08

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