A 2gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications

I. Chyn Wey; Lung Hao Chang; You Gang Chen; Shih Hung Chang; An Yeu Wu

doi:10.1109/ISCAS.2005.1464778

A 2gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications

I. Chyn Wey^*, Lung Hao Chang, You Gang Chen, Shih Hung Chang, An Yeu Wu

^*Corresponding author for this work

National Taiwan University

Research output: Contribution to journal › Conference article › peer-review

5 Scopus citations

Abstract

In this paper, a high-speed, scalable on-chip serial communication interface design is proposed. The serial communication clock frequency is designed to work correctly at 2.54GHz to provide 2Gb/s transmission bandwidth for SoC applications. By using the dynamic control technology, we can generate a fast and reliable control signal to activate and stop the oscillation of ring oscillator. By using the single-phase pulse-triggered TSPC shift register design, we can provide wider timing constraint tolerant range to achieve high-speed on-chip serial transmission. Moreover, the shift register design is a scalable design. By using the proposed method, we can provide 3 times wider bandwidth as compared to the prior art design [6].

Original language	English
Article number	1464778
Pages (from-to)	1074-1077
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
DOIs	https://doi.org/10.1109/ISCAS.2005.1464778
State	Published - 2005
Externally published	Yes
Event	IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan Duration: 23 05 2005 → 26 05 2005

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10.1109/ISCAS.2005.1464778

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title = "A 2gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications",

abstract = "In this paper, a high-speed, scalable on-chip serial communication interface design is proposed. The serial communication clock frequency is designed to work correctly at 2.54GHz to provide 2Gb/s transmission bandwidth for SoC applications. By using the dynamic control technology, we can generate a fast and reliable control signal to activate and stop the oscillation of ring oscillator. By using the single-phase pulse-triggered TSPC shift register design, we can provide wider timing constraint tolerant range to achieve high-speed on-chip serial transmission. Moreover, the shift register design is a scalable design. By using the proposed method, we can provide 3 times wider bandwidth as compared to the prior art design [6].",

author = "Wey, {I. Chyn} and Chang, {Lung Hao} and Chen, {You Gang} and Chang, {Shih Hung} and Wu, {An Yeu}",

year = "2005",

doi = "10.1109/ISCAS.2005.1464778",

language = "英语",

pages = "1074--1077",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 ; Conference date: 23-05-2005 Through 26-05-2005",

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TY - JOUR

T1 - A 2gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications

AU - Wey, I. Chyn

AU - Chang, Lung Hao

AU - Chen, You Gang

AU - Chang, Shih Hung

AU - Wu, An Yeu

PY - 2005

Y1 - 2005

N2 - In this paper, a high-speed, scalable on-chip serial communication interface design is proposed. The serial communication clock frequency is designed to work correctly at 2.54GHz to provide 2Gb/s transmission bandwidth for SoC applications. By using the dynamic control technology, we can generate a fast and reliable control signal to activate and stop the oscillation of ring oscillator. By using the single-phase pulse-triggered TSPC shift register design, we can provide wider timing constraint tolerant range to achieve high-speed on-chip serial transmission. Moreover, the shift register design is a scalable design. By using the proposed method, we can provide 3 times wider bandwidth as compared to the prior art design [6].

AB - In this paper, a high-speed, scalable on-chip serial communication interface design is proposed. The serial communication clock frequency is designed to work correctly at 2.54GHz to provide 2Gb/s transmission bandwidth for SoC applications. By using the dynamic control technology, we can generate a fast and reliable control signal to activate and stop the oscillation of ring oscillator. By using the single-phase pulse-triggered TSPC shift register design, we can provide wider timing constraint tolerant range to achieve high-speed on-chip serial transmission. Moreover, the shift register design is a scalable design. By using the proposed method, we can provide 3 times wider bandwidth as compared to the prior art design [6].

UR - http://www.scopus.com/inward/record.url?scp=67649088653&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2005.1464778

DO - 10.1109/ISCAS.2005.1464778

M3 - 会议文章

AN - SCOPUS:67649088653

SN - 0271-4310

SP - 1074

EP - 1077

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

M1 - 1464778

T2 - IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005

Y2 - 23 May 2005 through 26 May 2005

ER -

A 2gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications

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