Abstract
An anti-reset all-digital delay-locked loop (DLL) is presented. When the input clock frequency changes significantly, the dynamic frequency detector re-locks the DLL without any external reset signal. The proposed binary time-to-digital converter (BTDC) reduces effectively the hardware, compared with a conventional TDC. Unlike many previous all-digital DLLs, this one is a closed feedback loop that can track environmental variations. The input frequency range can be operated from 62.5-625 MHz. It spends at most six cycles to synchronize the input and output clocks.
Original language | English |
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Pages (from-to) | 566-570 |
Number of pages | 5 |
Journal | IEEE Transactions on Circuits and Systems II: Express Briefs |
Volume | 54 |
Issue number | 7 |
DOIs | |
State | Published - 07 07 2007 |
Externally published | Yes |
Keywords
- Delay-locked loop (DLL)
- lock detector
- time-to-digital con-verter(TDC)