A 62.5-625-MHz anti-reset all-digital delay-locked loop

Shao Ku Kao, Bo Jiun Chen, Shen Iuan Liu

Research output: Contribution to journalJournal Article peer-review

23 Scopus citations


An anti-reset all-digital delay-locked loop (DLL) is presented. When the input clock frequency changes significantly, the dynamic frequency detector re-locks the DLL without any external reset signal. The proposed binary time-to-digital converter (BTDC) reduces effectively the hardware, compared with a conventional TDC. Unlike many previous all-digital DLLs, this one is a closed feedback loop that can track environmental variations. The input frequency range can be operated from 62.5-625 MHz. It spends at most six cycles to synchronize the input and output clocks.

Original languageEnglish
Pages (from-to)566-570
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Issue number7
StatePublished - 07 07 2007
Externally publishedYes


  • Delay-locked loop (DLL)
  • lock detector
  • time-to-digital con-verter(TDC)


Dive into the research topics of 'A 62.5-625-MHz anti-reset all-digital delay-locked loop'. Together they form a unique fingerprint.

Cite this