A cmos active rectifier with time domain technique to enhance pce

Shao Ku Kao*

*Corresponding author for this work

Research output: Contribution to journalJournal Article peer-review

2 Scopus citations

Abstract

This paper presents a CMOS active rectifier with a time-domain technique to enhance power efficiency. A delay compensation circuit was designed using a time-domain technique. It converts the delay buffer’s delay time to a voltage value. The voltage is able to control on/off time in the comparator for variable input voltage. This circuit is designed in 0.18 m CMOS process. The input voltage range is from 2 V to 3.8 V with the output voltage from 1.8 V to 3.6 V. The efficiency can be maintained at more than 83% when the load is from 100 Ω to 1300 Ω for 3.3 V input voltage. The maximum efficiency is 90.3% at output power to be 109 mW for 3.3 V input voltage.

Original languageEnglish
Article number1450
JournalElectronics (Switzerland)
Volume10
Issue number12
DOIs
StatePublished - 02 06 2021

Bibliographical note

Publisher Copyright:
© 2021 by the author. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

Keywords

  • Current compensation
  • Delay compensation
  • PCE
  • Phase error detector
  • Wireless power transfer

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