A compact and general-purpose neural chip with electrically programmable synapses

Bang W. Lee; Bing J. Sheu

A compact and general-purpose neural chip with electrically programmable synapses

Bang W. Lee^*, Bing J. Sheu

^*Corresponding author for this work

University of Southern California

Research output: Contribution to journal › Conference article › peer-review

6 Scopus citations

Abstract

A neural chip with 64 neurons and 4096 DRAM-like programmable synapses has been designed and fabricated in 29 mm² area using the 2-μm scalable CMOS process from MOSIS Service. With 0.2-s refresh cycle, 8-b accuracy in synapses can be achieved for image processing. A system simulation result of image restoration using the programmable synapse chip architecture is also presented. An industrial-level 500-neuron chip with the fully connected synapse array can be implemented in 1-μm CMOS technologies.

Original language	English
Journal	Proceedings of the Custom Integrated Circuits Conference
State	Published - 1990
Externally published	Yes
Event	Proceedings of the 12th Annual IEEE 1990 Custom Integrated Circuits Conference - CICC '90 - Boston, MA, USA Duration: 13 05 1990 → 16 05 1990

Cite this

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title = "A compact and general-purpose neural chip with electrically programmable synapses",

abstract = "A neural chip with 64 neurons and 4096 DRAM-like programmable synapses has been designed and fabricated in 29 mm2 area using the 2-μm scalable CMOS process from MOSIS Service. With 0.2-s refresh cycle, 8-b accuracy in synapses can be achieved for image processing. A system simulation result of image restoration using the programmable synapse chip architecture is also presented. An industrial-level 500-neuron chip with the fully connected synapse array can be implemented in 1-μm CMOS technologies.",

author = "Lee, {Bang W.} and Sheu, {Bing J.}",

year = "1990",

language = "英语",

journal = "Proceedings of the Custom Integrated Circuits Conference",

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note = "Proceedings of the 12th Annual IEEE 1990 Custom Integrated Circuits Conference - CICC '90 ; Conference date: 13-05-1990 Through 16-05-1990",

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AU - Lee, Bang W.

AU - Sheu, Bing J.

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AB - A neural chip with 64 neurons and 4096 DRAM-like programmable synapses has been designed and fabricated in 29 mm2 area using the 2-μm scalable CMOS process from MOSIS Service. With 0.2-s refresh cycle, 8-b accuracy in synapses can be achieved for image processing. A system simulation result of image restoration using the programmable synapse chip architecture is also presented. An industrial-level 500-neuron chip with the fully connected synapse array can be implemented in 1-μm CMOS technologies.

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M3 - 会议文章

AN - SCOPUS:0025592949

SN - 0886-5930

JO - Proceedings of the Custom Integrated Circuits Conference

JF - Proceedings of the Custom Integrated Circuits Conference

T2 - Proceedings of the 12th Annual IEEE 1990 Custom Integrated Circuits Conference - CICC '90

Y2 - 13 May 1990 through 16 May 1990

ER -

A compact and general-purpose neural chip with electrically programmable synapses

Abstract

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