A compact-size dual-band (tri-mode) receiver front-end with switched harmonic mixer and technology scaling

Hsien Ku Chen; Kuan Ting Lin; Tao Wang; Shey Shi Lu

doi:10.1109/RFIC.2011.5940694

A compact-size dual-band (tri-mode) receiver front-end with switched harmonic mixer and technology scaling

Hsien Ku Chen^*
, Kuan Ting Lin
, Tao Wang
, Shey Shi Lu

^*Corresponding author for this work

Department of Electronic Engineering

National Taiwan University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

In this paper, a new dual-band receiver frontend for 2.5GHz and 4.9 to 5.9GHz is proposed in 90nm CMOS technology. The proposed receiver front-end embraces a 2.5/5∼6GHz dual-band low noise amplifier (LNA), a switchable harmonic mixer, an octuple-phase generator, and a wideband 10GHz phase locked-loop. By scaling LC VCO with constant performance, the chip size for LO part is reduced readily. The receiver front-end has 27.5/26.5dB of conversion gain, -28/-27dBm of P_1dB, -16/-16.5dBm of IIP3, and 10.2/9dBm of IIP2 in 2.5/5∼6GHz bands. The power consumption of the receiver and the PLL are 42mW and 18mW, respectively under 1.2V supply voltage. Such a low power dissipation is due to short routing path of the new proposed frequency planning.

Original language	English
Title of host publication	2011 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2011 - Digest of Papers
DOIs	https://doi.org/10.1109/RFIC.2011.5940694
State	Published - 2011
Event	2011 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2011 - Baltimore, MD, United States Duration: 05 06 2011 → 07 06 2011

Publication series

Name	Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
ISSN (Print)	1529-2517

Conference

Conference	2011 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2011
Country/Territory	United States
City	Baltimore, MD
Period	05/06/11 → 07/06/11

Keywords

dual-mode
mixer
phase-locked loop (PLL)
quality factor compensation
receiver
subharmonic
switched capacitor
switched inductor
technology scaling

Access to Document

10.1109/RFIC.2011.5940694

Cite this

Chen, H. K., Lin, K. T., Wang, T., & Lu, S. S. (2011). A compact-size dual-band (tri-mode) receiver front-end with switched harmonic mixer and technology scaling. In 2011 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2011 - Digest of Papers Article 5940694 (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium). https://doi.org/10.1109/RFIC.2011.5940694

@inproceedings{0de5c1d8907741e6b8f53323ba72f6b1,

title = "A compact-size dual-band (tri-mode) receiver front-end with switched harmonic mixer and technology scaling",

abstract = "In this paper, a new dual-band receiver frontend for 2.5GHz and 4.9 to 5.9GHz is proposed in 90nm CMOS technology. The proposed receiver front-end embraces a 2.5/5∼6GHz dual-band low noise amplifier (LNA), a switchable harmonic mixer, an octuple-phase generator, and a wideband 10GHz phase locked-loop. By scaling LC VCO with constant performance, the chip size for LO part is reduced readily. The receiver front-end has 27.5/26.5dB of conversion gain, -28/-27dBm of P1dB, -16/-16.5dBm of IIP3, and 10.2/9dBm of IIP2 in 2.5/5∼6GHz bands. The power consumption of the receiver and the PLL are 42mW and 18mW, respectively under 1.2V supply voltage. Such a low power dissipation is due to short routing path of the new proposed frequency planning.",

keywords = "dual-mode, mixer, phase-locked loop (PLL), quality factor compensation, receiver, subharmonic, switched capacitor, switched inductor, technology scaling",

author = "Chen, \{Hsien Ku\} and Lin, \{Kuan Ting\} and Tao Wang and Lu, \{Shey Shi\}",

year = "2011",

doi = "10.1109/RFIC.2011.5940694",

language = "英语",

isbn = "9781424482931",

series = "Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium",

booktitle = "2011 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2011 - Digest of Papers",

note = "2011 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2011 ; Conference date: 05-06-2011 Through 07-06-2011",

}

Chen, HK, Lin, KT, Wang, T & Lu, SS 2011, A compact-size dual-band (tri-mode) receiver front-end with switched harmonic mixer and technology scaling. in 2011 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2011 - Digest of Papers., 5940694, Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium, 2011 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2011, Baltimore, MD, United States, 05/06/11. https://doi.org/10.1109/RFIC.2011.5940694

A compact-size dual-band (tri-mode) receiver front-end with switched harmonic mixer and technology scaling. / Chen, Hsien Ku; Lin, Kuan Ting; Wang, Tao et al.
2011 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2011 - Digest of Papers. 2011. 5940694 (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A compact-size dual-band (tri-mode) receiver front-end with switched harmonic mixer and technology scaling

AU - Chen, Hsien Ku

AU - Lin, Kuan Ting

AU - Wang, Tao

AU - Lu, Shey Shi

PY - 2011

Y1 - 2011

N2 - In this paper, a new dual-band receiver frontend for 2.5GHz and 4.9 to 5.9GHz is proposed in 90nm CMOS technology. The proposed receiver front-end embraces a 2.5/5∼6GHz dual-band low noise amplifier (LNA), a switchable harmonic mixer, an octuple-phase generator, and a wideband 10GHz phase locked-loop. By scaling LC VCO with constant performance, the chip size for LO part is reduced readily. The receiver front-end has 27.5/26.5dB of conversion gain, -28/-27dBm of P1dB, -16/-16.5dBm of IIP3, and 10.2/9dBm of IIP2 in 2.5/5∼6GHz bands. The power consumption of the receiver and the PLL are 42mW and 18mW, respectively under 1.2V supply voltage. Such a low power dissipation is due to short routing path of the new proposed frequency planning.

AB - In this paper, a new dual-band receiver frontend for 2.5GHz and 4.9 to 5.9GHz is proposed in 90nm CMOS technology. The proposed receiver front-end embraces a 2.5/5∼6GHz dual-band low noise amplifier (LNA), a switchable harmonic mixer, an octuple-phase generator, and a wideband 10GHz phase locked-loop. By scaling LC VCO with constant performance, the chip size for LO part is reduced readily. The receiver front-end has 27.5/26.5dB of conversion gain, -28/-27dBm of P1dB, -16/-16.5dBm of IIP3, and 10.2/9dBm of IIP2 in 2.5/5∼6GHz bands. The power consumption of the receiver and the PLL are 42mW and 18mW, respectively under 1.2V supply voltage. Such a low power dissipation is due to short routing path of the new proposed frequency planning.

KW - dual-mode

KW - mixer

KW - phase-locked loop (PLL)

KW - quality factor compensation

KW - receiver

KW - subharmonic

KW - switched capacitor

KW - switched inductor

KW - technology scaling

UR - https://www.scopus.com/pages/publications/79960790677

U2 - 10.1109/RFIC.2011.5940694

DO - 10.1109/RFIC.2011.5940694

M3 - 会议稿件

AN - SCOPUS:79960790677

SN - 9781424482931

T3 - Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium

BT - 2011 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2011 - Digest of Papers

T2 - 2011 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2011

Y2 - 5 June 2011 through 7 June 2011

ER -

A compact-size dual-band (tri-mode) receiver front-end with switched harmonic mixer and technology scaling

Abstract

Publication series

Conference

Keywords

Access to Document

Other files and links

Fingerprint

Cite this