A cost-effective 2-D discrete cosine transform processor with reconfigurable datapath

Yeong Kang Lai; Han Jen Hsu

A cost-effective 2-D discrete cosine transform processor with reconfigurable datapath

Yeong Kang Lai^*, Han Jen Hsu

^*Corresponding author for this work

National Chung Hsing University

Research output: Contribution to journal › Conference article › peer-review

4 Scopus citations

Abstract

In this paper, a cost-effective 2-D discrete cosine transform processor using reconfigurable datapath is described. The proposed architecture uses some multiplexers to reduce computational complexity. This processor operates 8 × 8 blocks. Unlike other direct methods, the proposed architecture is regular for VLSI implementation. The proposed 2-D DCT processor costs 38598 transistors with 100 MHz using 0.35 μm CMOS technology.

Original language	English
Pages (from-to)	II492-II495
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2
State	Published - 2003
Externally published	Yes
Event	Proceedings of the 2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand Duration: 25 05 2003 → 28 05 2003

Cite this

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title = "A cost-effective 2-D discrete cosine transform processor with reconfigurable datapath",

abstract = "In this paper, a cost-effective 2-D discrete cosine transform processor using reconfigurable datapath is described. The proposed architecture uses some multiplexers to reduce computational complexity. This processor operates 8 × 8 blocks. Unlike other direct methods, the proposed architecture is regular for VLSI implementation. The proposed 2-D DCT processor costs 38598 transistors with 100 MHz using 0.35 μm CMOS technology.",

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AB - In this paper, a cost-effective 2-D discrete cosine transform processor using reconfigurable datapath is described. The proposed architecture uses some multiplexers to reduce computational complexity. This processor operates 8 × 8 blocks. Unlike other direct methods, the proposed architecture is regular for VLSI implementation. The proposed 2-D DCT processor costs 38598 transistors with 100 MHz using 0.35 μm CMOS technology.

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M3 - 会议文章

AN - SCOPUS:0038422191

SN - 0271-4310

VL - 2

SP - II492-II495

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

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Y2 - 25 May 2003 through 28 May 2003

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A cost-effective 2-D discrete cosine transform processor with reconfigurable datapath

Abstract

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