Abstract
A decoding algorithm for triple-error-correcting binary BCH codes was described. The algorithm is capable of decoding a recieved bit without knowing the number of errors in the recieved vector or temporarily inverting the recieved bit. The hardware decoder was also presented which contains a recived buffer, three syndrome registers, a random access memory (ROM), some circuits for computing operations and a simple control circuit.
Original language | English |
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Pages (from-to) | 299-303 |
Number of pages | 5 |
Journal | Information Processing Letters |
Volume | 80 |
Issue number | 6 |
DOIs | |
State | Published - 31 12 2001 |
Keywords
- Algorithms
- BCH codes
- ROM
- Step-by-step decoding method