A decoding algorithm for triple-error-correcting binary BCH codes

Erl Huei Lu; Shao Wei Wu; Yi Chang Cheng

doi:10.1016/S0020-0190(01)00180-6

A decoding algorithm for triple-error-correcting binary BCH codes

Erl Huei Lu
, Shao Wei Wu
, Yi Chang Cheng

Department of Electrical Engineering

Chung Cheng Institute of Technology

Research output: Contribution to journal › Journal Article › peer-review

11 Scopus citations

Abstract

A decoding algorithm for triple-error-correcting binary BCH codes was described. The algorithm is capable of decoding a recieved bit without knowing the number of errors in the recieved vector or temporarily inverting the recieved bit. The hardware decoder was also presented which contains a recived buffer, three syndrome registers, a random access memory (ROM), some circuits for computing operations and a simple control circuit.

Original language	English
Pages (from-to)	299-303
Number of pages	5
Journal	Information Processing Letters
Volume	80
Issue number	6
DOIs	https://doi.org/10.1016/S0020-0190(01)00180-6
State	Published - 31 12 2001

Keywords

Algorithms
BCH codes
ROM
Step-by-step decoding method

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10.1016/S0020-0190(01)00180-6

Cite this

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title = "A decoding algorithm for triple-error-correcting binary BCH codes",

abstract = "A decoding algorithm for triple-error-correcting binary BCH codes was described. The algorithm is capable of decoding a recieved bit without knowing the number of errors in the recieved vector or temporarily inverting the recieved bit. The hardware decoder was also presented which contains a recived buffer, three syndrome registers, a random access memory (ROM), some circuits for computing operations and a simple control circuit.",

keywords = "Algorithms, BCH codes, ROM, Step-by-step decoding method",

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year = "2001",

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AU - Wu, Shao Wei

AU - Cheng, Yi Chang

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Y1 - 2001/12/31

N2 - A decoding algorithm for triple-error-correcting binary BCH codes was described. The algorithm is capable of decoding a recieved bit without knowing the number of errors in the recieved vector or temporarily inverting the recieved bit. The hardware decoder was also presented which contains a recived buffer, three syndrome registers, a random access memory (ROM), some circuits for computing operations and a simple control circuit.

AB - A decoding algorithm for triple-error-correcting binary BCH codes was described. The algorithm is capable of decoding a recieved bit without knowing the number of errors in the recieved vector or temporarily inverting the recieved bit. The hardware decoder was also presented which contains a recived buffer, three syndrome registers, a random access memory (ROM), some circuits for computing operations and a simple control circuit.

KW - Algorithms

KW - BCH codes

KW - ROM

KW - Step-by-step decoding method

UR - https://www.scopus.com/pages/publications/0035980877

U2 - 10.1016/S0020-0190(01)00180-6

DO - 10.1016/S0020-0190(01)00180-6

M3 - 文章

AN - SCOPUS:0035980877

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VL - 80

SP - 299

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JF - Information Processing Letters

IS - 6

ER -

A decoding algorithm for triple-error-correcting binary BCH codes

Abstract

Keywords

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