A defect-tolerant reconfigurable nanoarchitecture design for multimedia applications

In this paper, a defect-tolerant reconfigurable multimedia computing architecture for nanotechnologies is proposed. The reconfigurable nanoarchitecture is composed of the array-based function units, the flexible interconnection networks, and the on-chip memories. With these components, the architecture can perform not only 8-, 16-, 32-, and 64-bit simple operations but also some novel operations flexibly. The defect-tolerant reconfigurable nanoarchitecture also incorporates a high communication bandwidth interconnection networks that enables it to easily route around defects, has significant implications for any nanoscale multimedia computations. The kernel component of the reconfigurable computing (RC) engine is the general-purpose processing cluster (GPPC) array, which performs the data-parallelism operations efficiently using the SIMD instructions. For the efficient connectivity, the inter-GPPC-row reconfigurable network is also proposed to achieve the requirements of high flexibility, low complexity, small area, and short network delay. Owing to flexible reconfiguration, multimedia applications can be performed efficiently on the proposed defect-tolerant reconfigurable nanoarchitecture. This is the key to enabling the design of robust nanosystem.