A delay-locked loop with statistical background calibration

Shao Ku Kao; Shen Iuan Liu

doi:10.1109/TCSII.2008.925664

A delay-locked loop with statistical background calibration

Shao Ku Kao^*, Shen Iuan Liu

^*Corresponding author for this work

National Taiwan University

Research output: Contribution to journal › Journal Article › peer-review

6 Scopus citations

Abstract

A delay-locked loop (DLL) using a statistical background calibration circuit (SBCC) is presented. This SBCC is utilized to calibrate the charge pump. Eighty identical arbiters with random mismatch effectively measure the phase error between the input and output clocks. Therefore, the static phase error of the DLL is improved. The proposed DLL has been fabricated in 0.18-μm CMOS process. Its active area is 0.078 mm². The power dissipation is 35 mW for the supply of 1.8 V and the input clock of 1.2 GHz. This DLL operates from 900 MHz to 1.2 GHz. The measured static phase error is 15.45 and 2.92 ps without and with the SBCC, respectively at 1.2 GHz.

Original language	English
Pages (from-to)	961-965
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	55
Issue number	10
DOIs	https://doi.org/10.1109/TCSII.2008.925664
State	Published - 10 2008
Externally published	Yes

Keywords

Calibration
Charge pump (CP)
Delay-locked loop (DLL)
Phase error

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10.1109/TCSII.2008.925664

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title = "A delay-locked loop with statistical background calibration",

abstract = "A delay-locked loop (DLL) using a statistical background calibration circuit (SBCC) is presented. This SBCC is utilized to calibrate the charge pump. Eighty identical arbiters with random mismatch effectively measure the phase error between the input and output clocks. Therefore, the static phase error of the DLL is improved. The proposed DLL has been fabricated in 0.18-μm CMOS process. Its active area is 0.078 mm2. The power dissipation is 35 mW for the supply of 1.8 V and the input clock of 1.2 GHz. This DLL operates from 900 MHz to 1.2 GHz. The measured static phase error is 15.45 and 2.92 ps without and with the SBCC, respectively at 1.2 GHz.",

keywords = "Calibration, Charge pump (CP), Delay-locked loop (DLL), Phase error",

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AU - Kao, Shao Ku

AU - Liu, Shen Iuan

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N2 - A delay-locked loop (DLL) using a statistical background calibration circuit (SBCC) is presented. This SBCC is utilized to calibrate the charge pump. Eighty identical arbiters with random mismatch effectively measure the phase error between the input and output clocks. Therefore, the static phase error of the DLL is improved. The proposed DLL has been fabricated in 0.18-μm CMOS process. Its active area is 0.078 mm2. The power dissipation is 35 mW for the supply of 1.8 V and the input clock of 1.2 GHz. This DLL operates from 900 MHz to 1.2 GHz. The measured static phase error is 15.45 and 2.92 ps without and with the SBCC, respectively at 1.2 GHz.

AB - A delay-locked loop (DLL) using a statistical background calibration circuit (SBCC) is presented. This SBCC is utilized to calibrate the charge pump. Eighty identical arbiters with random mismatch effectively measure the phase error between the input and output clocks. Therefore, the static phase error of the DLL is improved. The proposed DLL has been fabricated in 0.18-μm CMOS process. Its active area is 0.078 mm2. The power dissipation is 35 mW for the supply of 1.8 V and the input clock of 1.2 GHz. This DLL operates from 900 MHz to 1.2 GHz. The measured static phase error is 15.45 and 2.92 ps without and with the SBCC, respectively at 1.2 GHz.

KW - Calibration

KW - Charge pump (CP)

KW - Delay-locked loop (DLL)

KW - Phase error

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JO - IEEE Transactions on Circuits and Systems II: Express Briefs

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A delay-locked loop with statistical background calibration

Abstract

Keywords

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