A fast-corrected all-digital DCC with synchronous input clock

Shao Ku Kao, Sheng Hung Hsueh*

*Corresponding author for this work

Research output: Contribution to journalJournal Article peer-review

1 Scopus citations


This paper presents a fast-corrected all-digital duty-cycle corrector (DCC) with synchronous input clock. The proposed DCC has many features, including fast locking in 4 cycles, wide range correction, and synchronous 50% duty-cycle clock with an input clock. The circuit can operate from 500 to 900 MHz and corrects a wide range of input duty cycle ranging from 25 to 75%. The duty-cycle error of the output clock is between -2.4 and 2.7%. The largest static phase error between the input and output clock is -44 ps at 900 MHz. The RMS and peak-to-peak jitters are 1.9 and 14.7 ps at 900 MHz, respectively. The proposed DCC is implemented in a 0.18-μm complementary metal oxide semiconductor process. The proposed DCC occupies an area of 0.05 mm2 and dissipates 23 mW with 1.8-V supply voltage at 900 MHz.

Original languageEnglish
Pages (from-to)1845-1860
Number of pages16
JournalInternational Journal of Circuit Theory and Applications
Issue number12
StatePublished - 01 12 2015

Bibliographical note

Publisher Copyright:
Copyright © 2014 John Wiley & Sons, Ltd.


  • DCC
  • all digital
  • duty cycle
  • fast locked
  • phase error
  • synchronization


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