A fast-locked all-digital delay-locked loop with non-50% input duty cycle

Shao Ku Kao; Bo Jiun Chen; Shen Iuan Liu

doi:10.1109/EDSSC.2007.4450326

A fast-locked all-digital delay-locked loop with non-50% input duty cycle

Shao Ku Kao^*
, Bo Jiun Chen
, Shen Iuan Liu

^*Corresponding author for this work

National Taiwan University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

A fast-locked all-digital delay-locked loop (DLL) with 50% output duty cycle is presented. A delay line using TSPC DFFs is re-used for the DLL and a time-to-digital converter. It results in a small-area and fast-locked DLL. The proposed DLL generates the output clock with 50% duty cycle in 4 cycles This DLL has been fabricated in a 0.18um process. The core area is 350um×105um. The measured input frequency range is from 300MHz to 500MHz with input duty cycle of 40%-60%.

Original language	English
Title of host publication	IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
Pages	1125-1128
Number of pages	4
DOIs	https://doi.org/10.1109/EDSSC.2007.4450326
State	Published - 2007
Externally published	Yes
Event	IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 - Tainan, Taiwan Duration: 20 12 2007 → 22 12 2007

Publication series

Name	IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007

Conference

Conference	IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
Country/Territory	Taiwan
City	Tainan
Period	20/12/07 → 22/12/07

Access to Document

10.1109/EDSSC.2007.4450326

Cite this

@inproceedings{e0b82c58b11444eea1e7f3b6e825ba85,

title = "A fast-locked all-digital delay-locked loop with non-50\% input duty cycle",

abstract = "A fast-locked all-digital delay-locked loop (DLL) with 50\% output duty cycle is presented. A delay line using TSPC DFFs is re-used for the DLL and a time-to-digital converter. It results in a small-area and fast-locked DLL. The proposed DLL generates the output clock with 50\% duty cycle in 4 cycles This DLL has been fabricated in a 0.18um process. The core area is 350um×105um. The measured input frequency range is from 300MHz to 500MHz with input duty cycle of 40\%-60\%.",

author = "Kao, \{Shao Ku\} and Chen, \{Bo Jiun\} and Liu, \{Shen Iuan\}",

year = "2007",

doi = "10.1109/EDSSC.2007.4450326",

language = "英语",

isbn = "1424406374",

series = "IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007",

pages = "1125--1128",

booktitle = "IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007",

note = "IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 ; Conference date: 20-12-2007 Through 22-12-2007",

}

Kao, SK, Chen, BJ & Liu, SI 2007, A fast-locked all-digital delay-locked loop with non-50% input duty cycle. in IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007., 4450326, IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007, pp. 1125-1128, IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007, Tainan, Taiwan, 20/12/07. https://doi.org/10.1109/EDSSC.2007.4450326

A fast-locked all-digital delay-locked loop with non-50% input duty cycle. / Kao, Shao Ku; Chen, Bo Jiun; Liu, Shen Iuan.
IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007. 2007. p. 1125-1128 4450326 (IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

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AU - Kao, Shao Ku

AU - Chen, Bo Jiun

AU - Liu, Shen Iuan

PY - 2007

Y1 - 2007

N2 - A fast-locked all-digital delay-locked loop (DLL) with 50% output duty cycle is presented. A delay line using TSPC DFFs is re-used for the DLL and a time-to-digital converter. It results in a small-area and fast-locked DLL. The proposed DLL generates the output clock with 50% duty cycle in 4 cycles This DLL has been fabricated in a 0.18um process. The core area is 350um×105um. The measured input frequency range is from 300MHz to 500MHz with input duty cycle of 40%-60%.

AB - A fast-locked all-digital delay-locked loop (DLL) with 50% output duty cycle is presented. A delay line using TSPC DFFs is re-used for the DLL and a time-to-digital converter. It results in a small-area and fast-locked DLL. The proposed DLL generates the output clock with 50% duty cycle in 4 cycles This DLL has been fabricated in a 0.18um process. The core area is 350um×105um. The measured input frequency range is from 300MHz to 500MHz with input duty cycle of 40%-60%.

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U2 - 10.1109/EDSSC.2007.4450326

DO - 10.1109/EDSSC.2007.4450326

M3 - 会议稿件

AN - SCOPUS:43049171820

SN - 1424406374

SN - 9781424406371

T3 - IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007

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EP - 1128

BT - IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007

T2 - IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007

Y2 - 20 December 2007 through 22 December 2007

ER -

A fast-locked all-digital delay-locked loop with non-50% input duty cycle

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