A fast locking-in and low jitter PLL with a process-immune locking-in monitor

In this brief, a digital-control adaptive phase-locked loop (PLL) with a digital locking-in monitor (LIM) consisting of a time-to-digital converter (TDC) and a bandwidth control unit (BCU) is proposed to reduce the locking time as well as to suppress the jitter when locked. It uses a delay-independent threshold in a dual-slope transfer function to detect the locked state according to the counting result of the proposed TDC, which feeds to the BCU to switch the bandwidth of PLL. Then the PLL is switched from a wide loop bandwidth (6 MHz) to a narrow bandwidth (3 MHz) in the locked state. To verify the proposed scheme, the proposed adaptive PLL is implemented in a TSMC 0.18 μ m 1P6M CMOS process with a supply voltage of 1.8 V. The measurement results show that the locking time is reduced by 67% while with a RMS jitter of only 8.79 ps when operating at 1.6 GHz.