A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time

Chia Tsun Wu; Wei Wang; I. Chyn Wey; An Yeu Wu

A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time

Chia Tsun Wu^*
, Wei Wang
, I. Chyn Wey
, An Yeu Wu

^*Corresponding author for this work

National Taiwan University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

This paper presents a Frequency-Estimation Algorithm for the ADPLL designs instead of traditional binary frequency-search algorithm. With the proposed ADPLL architecture and synchronization process, the lock time can be optimized to two cycles. As the reference clock varies or frequency multiplication switches, lock time holds in two reference clock cycles. An implementation of proposed ADPLL design is realized in UMC 0.18 μm 1P6M CMOS technology with core area of 520×530 μm². The PLL has the frequency range of 140 MHz to 1030 MHz with 22ps DCO resolution.

Original language	English
Title of host publication	ISCAS 2006
Subtitle of host publication	2006 IEEE International Symposium on Circuits and Systems, Proceedings
Pages	4082-4085
Number of pages	4
State	Published - 2006
Externally published	Yes
Event	ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Greece Duration: 21 05 2006 → 24 05 2006

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Conference

Conference	ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
Country/Territory	Greece
City	Kos
Period	21/05/06 → 24/05/06

Cite this

@inproceedings{5b390de6fc6c4d14927fc991a4abd715,

title = "A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time",

abstract = "This paper presents a Frequency-Estimation Algorithm for the ADPLL designs instead of traditional binary frequency-search algorithm. With the proposed ADPLL architecture and synchronization process, the lock time can be optimized to two cycles. As the reference clock varies or frequency multiplication switches, lock time holds in two reference clock cycles. An implementation of proposed ADPLL design is realized in UMC 0.18 μm 1P6M CMOS technology with core area of 520×530 μm2. The PLL has the frequency range of 140 MHz to 1030 MHz with 22ps DCO resolution.",

author = "Wu, \{Chia Tsun\} and Wei Wang and Wey, \{I. Chyn\} and Wu, \{An Yeu\}",

year = "2006",

language = "英语",

isbn = "0780393902",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

pages = "4082--4085",

booktitle = "ISCAS 2006",

note = "ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems ; Conference date: 21-05-2006 Through 24-05-2006",

}

Wu, CT, Wang, W, Wey, IC & Wu, AY 2006, A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time. in ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings., 1693526, Proceedings - IEEE International Symposium on Circuits and Systems, pp. 4082-4085, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Kos, Greece, 21/05/06.

A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time. / Wu, Chia Tsun; Wang, Wei; Wey, I. Chyn et al.
ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings. 2006. p. 4082-4085 1693526 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time

AU - Wu, Chia Tsun

AU - Wang, Wei

AU - Wey, I. Chyn

AU - Wu, An Yeu

PY - 2006

Y1 - 2006

N2 - This paper presents a Frequency-Estimation Algorithm for the ADPLL designs instead of traditional binary frequency-search algorithm. With the proposed ADPLL architecture and synchronization process, the lock time can be optimized to two cycles. As the reference clock varies or frequency multiplication switches, lock time holds in two reference clock cycles. An implementation of proposed ADPLL design is realized in UMC 0.18 μm 1P6M CMOS technology with core area of 520×530 μm2. The PLL has the frequency range of 140 MHz to 1030 MHz with 22ps DCO resolution.

AB - This paper presents a Frequency-Estimation Algorithm for the ADPLL designs instead of traditional binary frequency-search algorithm. With the proposed ADPLL architecture and synchronization process, the lock time can be optimized to two cycles. As the reference clock varies or frequency multiplication switches, lock time holds in two reference clock cycles. An implementation of proposed ADPLL design is realized in UMC 0.18 μm 1P6M CMOS technology with core area of 520×530 μm2. The PLL has the frequency range of 140 MHz to 1030 MHz with 22ps DCO resolution.

UR - https://www.scopus.com/pages/publications/34547247708

M3 - 会议稿件

AN - SCOPUS:34547247708

SN - 0780393902

SN - 9780780393905

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

SP - 4082

EP - 4085

BT - ISCAS 2006

T2 - ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems

Y2 - 21 May 2006 through 24 May 2006

ER -

A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time

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