A high resolution FPGA-based merged delay line TDC with nonlinearity calibration

Yuan Ho Chen

doi:10.1109/ISCAS.2013.6572370

A high resolution FPGA-based merged delay line TDC with nonlinearity calibration

Yuan Ho Chen^*

^*Corresponding author for this work

Chung Yuan Christian University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

12 Scopus citations

Abstract

This paper proposes a merged delay line (MDL) field-programmable gate array (FPGA) based time-to-digital converter (TDC). Instead of traditional tapped delay line (TDL), the proposed MDL-TDC merges several small delay cells to improve the linearity performance effectively. Implemented in a Xilinx XC5VLX110T-1FF1136 FPGA device, the proposed MDL-TDC has 50 ps time resolution, and the ranges of differential non-linearity (DNL) and integral non-linearity (INL) can be reduced 16.6% and 5.4% as compared with traditional one, respectively. Furthermore, 29 ps root-mean-square (RMS) is measured for the proposed MDL-TDC inputting a constant delay source. Therefore, the proposed MDL-TDC is recommended to implement in FPGA-based TDC achieving a high-resolution time and linearity performance.

Original language	English
Title of host publication	2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
Pages	2432-2435
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2013.6572370
State	Published - 2013
Externally published	Yes
Event	2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013 - Beijing, China Duration: 19 05 2013 → 23 05 2013

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Conference

Conference	2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
Country/Territory	China
City	Beijing
Period	19/05/13 → 23/05/13

Keywords

Differential non-linearity
Field-programmable gate array
Merged delay line
Time-to-digital converter

Access to Document

10.1109/ISCAS.2013.6572370

Cite this

@inproceedings{ca2401b833044472932a22c5c013ecfa,

title = "A high resolution FPGA-based merged delay line TDC with nonlinearity calibration",

abstract = "This paper proposes a merged delay line (MDL) field-programmable gate array (FPGA) based time-to-digital converter (TDC). Instead of traditional tapped delay line (TDL), the proposed MDL-TDC merges several small delay cells to improve the linearity performance effectively. Implemented in a Xilinx XC5VLX110T-1FF1136 FPGA device, the proposed MDL-TDC has 50 ps time resolution, and the ranges of differential non-linearity (DNL) and integral non-linearity (INL) can be reduced 16.6% and 5.4% as compared with traditional one, respectively. Furthermore, 29 ps root-mean-square (RMS) is measured for the proposed MDL-TDC inputting a constant delay source. Therefore, the proposed MDL-TDC is recommended to implement in FPGA-based TDC achieving a high-resolution time and linearity performance.",

keywords = "Differential non-linearity, Field-programmable gate array, Merged delay line, Time-to-digital converter",

author = "Chen, {Yuan Ho}",

year = "2013",

doi = "10.1109/ISCAS.2013.6572370",

language = "英语",

isbn = "9781467357609",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

pages = "2432--2435",

booktitle = "2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013",

note = "2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013 ; Conference date: 19-05-2013 Through 23-05-2013",

}

Chen, YH 2013, A high resolution FPGA-based merged delay line TDC with nonlinearity calibration. in 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013., 6572370, Proceedings - IEEE International Symposium on Circuits and Systems, pp. 2432-2435, 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013, Beijing, China, 19/05/13. https://doi.org/10.1109/ISCAS.2013.6572370

A high resolution FPGA-based merged delay line TDC with nonlinearity calibration. / Chen, Yuan Ho.
2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013. 2013. p. 2432-2435 6572370 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A high resolution FPGA-based merged delay line TDC with nonlinearity calibration

AU - Chen, Yuan Ho

PY - 2013

Y1 - 2013

N2 - This paper proposes a merged delay line (MDL) field-programmable gate array (FPGA) based time-to-digital converter (TDC). Instead of traditional tapped delay line (TDL), the proposed MDL-TDC merges several small delay cells to improve the linearity performance effectively. Implemented in a Xilinx XC5VLX110T-1FF1136 FPGA device, the proposed MDL-TDC has 50 ps time resolution, and the ranges of differential non-linearity (DNL) and integral non-linearity (INL) can be reduced 16.6% and 5.4% as compared with traditional one, respectively. Furthermore, 29 ps root-mean-square (RMS) is measured for the proposed MDL-TDC inputting a constant delay source. Therefore, the proposed MDL-TDC is recommended to implement in FPGA-based TDC achieving a high-resolution time and linearity performance.

AB - This paper proposes a merged delay line (MDL) field-programmable gate array (FPGA) based time-to-digital converter (TDC). Instead of traditional tapped delay line (TDL), the proposed MDL-TDC merges several small delay cells to improve the linearity performance effectively. Implemented in a Xilinx XC5VLX110T-1FF1136 FPGA device, the proposed MDL-TDC has 50 ps time resolution, and the ranges of differential non-linearity (DNL) and integral non-linearity (INL) can be reduced 16.6% and 5.4% as compared with traditional one, respectively. Furthermore, 29 ps root-mean-square (RMS) is measured for the proposed MDL-TDC inputting a constant delay source. Therefore, the proposed MDL-TDC is recommended to implement in FPGA-based TDC achieving a high-resolution time and linearity performance.

KW - Differential non-linearity

KW - Field-programmable gate array

KW - Merged delay line

KW - Time-to-digital converter

UR - http://www.scopus.com/inward/record.url?scp=84883330424&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2013.6572370

DO - 10.1109/ISCAS.2013.6572370

M3 - 会议稿件

AN - SCOPUS:84883330424

SN - 9781467357609

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

SP - 2432

EP - 2435

BT - 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013

T2 - 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013

Y2 - 19 May 2013 through 23 May 2013

ER -

A high resolution FPGA-based merged delay line TDC with nonlinearity calibration

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