A High Slew-Rate CMOS Amplifier for Analog Signal Processing

Bang W. Lee; Bing J. Sheu

doi:10.1109/4.102692

A High Slew-Rate CMOS Amplifier for Analog Signal Processing

Bang W. Lee
, Bing J. Sheu

Research output: Contribution to journal › Journal Article › peer-review

30 Scopus citations

Abstract

The performance of several types of analog VLSI circuits is limited by the settling behavior of CMOS amplifiers. An amplifier with a nonsaturated input stage which achieves a high slew-rate response is presented. The impact of this high slew-rate amplifier on switched-capacitor circuits is described. Prototyping amplifier circuits were fabricated by the MOSIS Service using a 2-μm scalable CMOS technology. When biased at the dc power dissipation of 1 mW, the two-stage amplifier achieves a slew rate of 80 V/μs, a positive-supply rejection ratio of 73 dB, and a negative-supply rejection ratio of 57 dB at 50 kHz.

Original language	English
Pages (from-to)	885-889
Number of pages	5
Journal	IEEE Journal of Solid-State Circuits
Volume	25
Issue number	3
DOIs	https://doi.org/10.1109/4.102692
State	Published - 06 1990
Externally published	Yes

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abstract = "The performance of several types of analog VLSI circuits is limited by the settling behavior of CMOS amplifiers. An amplifier with a nonsaturated input stage which achieves a high slew-rate response is presented. The impact of this high slew-rate amplifier on switched-capacitor circuits is described. Prototyping amplifier circuits were fabricated by the MOSIS Service using a 2-μm scalable CMOS technology. When biased at the dc power dissipation of 1 mW, the two-stage amplifier achieves a slew rate of 80 V/μs, a positive-supply rejection ratio of 73 dB, and a negative-supply rejection ratio of 57 dB at 50 kHz.",

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AB - The performance of several types of analog VLSI circuits is limited by the settling behavior of CMOS amplifiers. An amplifier with a nonsaturated input stage which achieves a high slew-rate response is presented. The impact of this high slew-rate amplifier on switched-capacitor circuits is described. Prototyping amplifier circuits were fabricated by the MOSIS Service using a 2-μm scalable CMOS technology. When biased at the dc power dissipation of 1 mW, the two-stage amplifier achieves a slew rate of 80 V/μs, a positive-supply rejection ratio of 73 dB, and a negative-supply rejection ratio of 57 dB at 50 kHz.

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A High Slew-Rate CMOS Amplifier for Analog Signal Processing

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