A high-speed, high fan-in dynamic comparator with low transistor count

I. Chyn Wey*, Tz Cheng He, Hwang Cherng Chow, Pie Hsien Sun, Chien Chang Peng

*Corresponding author for this work

Research output: Contribution to journalJournal Article peer-review

4 Scopus citations

Abstract

In this article, we proposed a high-speed, high fan-in dynamic CMOS comparator with low transistor count. Our approach is to construct the dynamic comparator based on the prior superiority of dynamic CMOS comparator and to further enhance its operating speed. Constructing the comparator with dynamic CMOS architecture, we can save 63.2% transistor count as compared with the conventional static CMOS design. The main contribution to accelerate the speed of dynamic comparator is to solve the problem of weak 0 existing in the PMOS of pull-down network. Instead, as an alternate to PMOS in the pull-down network, we use NMOS combined with an additional inverter in the front of the NMOS input gate. In this way, we can perform the same function as PMOS, but transmitting with both good 1 and good 0. As a result, the proposed dynamic comparator can operate with lower propagation delay in the pull-down network. Finally, the proposed 64-bit dynamic comparator circuit can operate correctly under a clock frequency of 450 MHz with 0.18 m technology while the prior circuit can only operate under 250 MHz at the same time.

Original languageEnglish
Pages (from-to)681-690
Number of pages10
JournalInternational Journal of Electronics
Volume101
Issue number5
DOIs
StatePublished - 04 05 2014

Keywords

  • CMOS
  • comparator
  • dynamic circuit
  • high fan-in
  • high speed
  • low transistor count

Fingerprint

Dive into the research topics of 'A high-speed, high fan-in dynamic comparator with low transistor count'. Together they form a unique fingerprint.

Cite this