A high-speed scalable shift-register based on-chip serial communication design for SoC applications

I. Chyn Wey; You Gang Chen; Chia Tsun Wu; Wei Wang; An Yeu Wu

doi:10.1109/RME.2005.1543012

A high-speed scalable shift-register based on-chip serial communication design for SoC applications

I. Chyn Wey^*
, You Gang Chen
, Chia Tsun Wu
, Wei Wang
, An Yeu Wu

^*Corresponding author for this work

National Taiwan University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this paper, a high-speed, scalable on-chip serial transmission design is proposed to provide 2Gb/s transmission bandwidth for SoC applications. By using the dynamic control technology and the single-phase pulse-triggered TSPC shift register design, we can provide high-speed on-chip serial transmission. Moreover, the shift register design is a scalable design. By using the proposed method, we can provide 3 times wider bandwidth as compared to the prior art design [6].

Original language	English
Title of host publication	2005 PhD Research in Microelectronics and Electronics - Proceedingsof the Conference
Pages	67-70
Number of pages	4
DOIs	https://doi.org/10.1109/RME.2005.1543012
State	Published - 2005
Externally published	Yes
Event	2005 PhD Research in Microelectronics and Electronics Conference - Lausanne, Switzerland Duration: 25 07 2005 → 28 07 2005

Publication series

Name	2005 PhD Research in Microelectronics and Electronics - Proceedingsof the Conference
Volume	I

Conference

Conference	2005 PhD Research in Microelectronics and Electronics Conference
Country/Territory	Switzerland
City	Lausanne
Period	25/07/05 → 28/07/05

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10.1109/RME.2005.1543012

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Wey, I. C., Chen, Y. G., Wu, C. T., Wang, W., & Wu, A. Y. (2005). A high-speed scalable shift-register based on-chip serial communication design for SoC applications. In 2005 PhD Research in Microelectronics and Electronics - Proceedingsof the Conference (pp. 67-70). Article 1543012 (2005 PhD Research in Microelectronics and Electronics - Proceedingsof the Conference; Vol. I). https://doi.org/10.1109/RME.2005.1543012

@inproceedings{65d933ac3aa14de0b0600a65e6e50fbc,

title = "A high-speed scalable shift-register based on-chip serial communication design for SoC applications",

abstract = "In this paper, a high-speed, scalable on-chip serial transmission design is proposed to provide 2Gb/s transmission bandwidth for SoC applications. By using the dynamic control technology and the single-phase pulse-triggered TSPC shift register design, we can provide high-speed on-chip serial transmission. Moreover, the shift register design is a scalable design. By using the proposed method, we can provide 3 times wider bandwidth as compared to the prior art design [6].",

author = "Wey, \{I. Chyn\} and Chen, \{You Gang\} and Wu, \{Chia Tsun\} and Wei Wang and Wu, \{An Yeu\}",

year = "2005",

doi = "10.1109/RME.2005.1543012",

language = "英语",

isbn = "0780393457",

series = "2005 PhD Research in Microelectronics and Electronics - Proceedingsof the Conference",

pages = "67--70",

booktitle = "2005 PhD Research in Microelectronics and Electronics - Proceedingsof the Conference",

note = "2005 PhD Research in Microelectronics and Electronics Conference ; Conference date: 25-07-2005 Through 28-07-2005",

}

Wey, IC, Chen, YG, Wu, CT, Wang, W & Wu, AY 2005, A high-speed scalable shift-register based on-chip serial communication design for SoC applications. in 2005 PhD Research in Microelectronics and Electronics - Proceedingsof the Conference., 1543012, 2005 PhD Research in Microelectronics and Electronics - Proceedingsof the Conference, vol. I, pp. 67-70, 2005 PhD Research in Microelectronics and Electronics Conference, Lausanne, Switzerland, 25/07/05. https://doi.org/10.1109/RME.2005.1543012

A high-speed scalable shift-register based on-chip serial communication design for SoC applications. / Wey, I. Chyn; Chen, You Gang; Wu, Chia Tsun et al.
2005 PhD Research in Microelectronics and Electronics - Proceedingsof the Conference. 2005. p. 67-70 1543012 (2005 PhD Research in Microelectronics and Electronics - Proceedingsof the Conference; Vol. I).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - A high-speed scalable shift-register based on-chip serial communication design for SoC applications

AU - Wey, I. Chyn

AU - Chen, You Gang

AU - Wu, Chia Tsun

AU - Wang, Wei

AU - Wu, An Yeu

PY - 2005

Y1 - 2005

N2 - In this paper, a high-speed, scalable on-chip serial transmission design is proposed to provide 2Gb/s transmission bandwidth for SoC applications. By using the dynamic control technology and the single-phase pulse-triggered TSPC shift register design, we can provide high-speed on-chip serial transmission. Moreover, the shift register design is a scalable design. By using the proposed method, we can provide 3 times wider bandwidth as compared to the prior art design [6].

AB - In this paper, a high-speed, scalable on-chip serial transmission design is proposed to provide 2Gb/s transmission bandwidth for SoC applications. By using the dynamic control technology and the single-phase pulse-triggered TSPC shift register design, we can provide high-speed on-chip serial transmission. Moreover, the shift register design is a scalable design. By using the proposed method, we can provide 3 times wider bandwidth as compared to the prior art design [6].

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DO - 10.1109/RME.2005.1543012

M3 - 会议稿件

AN - SCOPUS:33750294059

SN - 0780393457

SN - 9780780393455

T3 - 2005 PhD Research in Microelectronics and Electronics - Proceedingsof the Conference

SP - 67

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BT - 2005 PhD Research in Microelectronics and Electronics - Proceedingsof the Conference

T2 - 2005 PhD Research in Microelectronics and Electronics Conference

Y2 - 25 July 2005 through 28 July 2005

ER -

Wey IC, Chen YG, Wu CT, Wang W, Wu AY. A high-speed scalable shift-register based on-chip serial communication design for SoC applications. In 2005 PhD Research in Microelectronics and Electronics - Proceedingsof the Conference. 2005. p. 67-70. 1543012. (2005 PhD Research in Microelectronics and Electronics - Proceedingsof the Conference). doi: 10.1109/RME.2005.1543012

A high-speed scalable shift-register based on-chip serial communication design for SoC applications

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