A knowledge-based program for compacting mask layout of integrated circuits

Pei Yung Hsiao*, S. F.Steven Chen, Chia Chun Tsai, Wu Shiung Feng

*Corresponding author for this work

Research output: Contribution to journalJournal Article peer-review

1 Scopus citations


Recent research in knowledge-based expert systems for VLSI tools' design has concentrated on floor-planning, placement, routing, and cell generation. The paper describes a knowledge-based scanning-line approach to VLSI layout compaction. This approach differs from traditional algorithmic approaches: an expert compactor interprets constraints by production rules in a more 'intelligent' way. Experimental results show that the presented system can compete with conventional algorithmic approaches.

Original languageEnglish
Pages (from-to)223-231
Number of pages9
JournalCAD Computer Aided Design
Issue number3
StatePublished - 04 1991
Externally publishedYes


  • VLSI-CAD tools
  • computer-aided design
  • knowledge-based system
  • layout compaction


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