Abstract
Recent research in knowledge-based expert systems for VLSI tools' design has concentrated on floor-planning, placement, routing, and cell generation. The paper describes a knowledge-based scanning-line approach to VLSI layout compaction. This approach differs from traditional algorithmic approaches: an expert compactor interprets constraints by production rules in a more 'intelligent' way. Experimental results show that the presented system can compete with conventional algorithmic approaches.
Original language | English |
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Pages (from-to) | 223-231 |
Number of pages | 9 |
Journal | CAD Computer Aided Design |
Volume | 23 |
Issue number | 3 |
DOIs | |
State | Published - 04 1991 |
Externally published | Yes |
Keywords
- VLSI-CAD tools
- computer-aided design
- knowledge-based system
- layout compaction