A knowledge-based program for compacting mask layout of integrated circuits

Pei Yung Hsiao; S. F.Steven Chen; Chia Chun Tsai; Wu Shiung Feng

doi:10.1016/0010-4485(91)90092-B

A knowledge-based program for compacting mask layout of integrated circuits

Pei Yung Hsiao^*
, S. F.Steven Chen
, Chia Chun Tsai
, Wu Shiung Feng

^*Corresponding author for this work

National Taiwan University

Research output: Contribution to journal › Journal Article › peer-review

1 Scopus citations

Abstract

Recent research in knowledge-based expert systems for VLSI tools' design has concentrated on floor-planning, placement, routing, and cell generation. The paper describes a knowledge-based scanning-line approach to VLSI layout compaction. This approach differs from traditional algorithmic approaches: an expert compactor interprets constraints by production rules in a more 'intelligent' way. Experimental results show that the presented system can compete with conventional algorithmic approaches.

Original language	English
Pages (from-to)	223-231
Number of pages	9
Journal	CAD Computer Aided Design
Volume	23
Issue number	3
DOIs	https://doi.org/10.1016/0010-4485(91)90092-B
State	Published - 04 1991
Externally published	Yes

Keywords

VLSI-CAD tools
computer-aided design
knowledge-based system
layout compaction

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10.1016/0010-4485(91)90092-B

Cite this

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abstract = "Recent research in knowledge-based expert systems for VLSI tools' design has concentrated on floor-planning, placement, routing, and cell generation. The paper describes a knowledge-based scanning-line approach to VLSI layout compaction. This approach differs from traditional algorithmic approaches: an expert compactor interprets constraints by production rules in a more 'intelligent' way. Experimental results show that the presented system can compete with conventional algorithmic approaches.",

keywords = "VLSI-CAD tools, computer-aided design, knowledge-based system, layout compaction",

author = "Hsiao, \{Pei Yung\} and Chen, \{S. F.Steven\} and Tsai, \{Chia Chun\} and Feng, \{Wu Shiung\}",

year = "1991",

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N2 - Recent research in knowledge-based expert systems for VLSI tools' design has concentrated on floor-planning, placement, routing, and cell generation. The paper describes a knowledge-based scanning-line approach to VLSI layout compaction. This approach differs from traditional algorithmic approaches: an expert compactor interprets constraints by production rules in a more 'intelligent' way. Experimental results show that the presented system can compete with conventional algorithmic approaches.

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KW - VLSI-CAD tools

KW - computer-aided design

KW - knowledge-based system

KW - layout compaction

UR - https://www.scopus.com/pages/publications/0026142569

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A knowledge-based program for compacting mask layout of integrated circuits

Abstract

Keywords

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