A lane departure warning system with FPGA modular design

Pei Yung Hsiao, Jin Hua Hong*, Chia Chen Hsu, Hsiao Ping Lin, Shih Shinh Huang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

The visual based Lane Departure Warning System (LDWS) is one of the emerging systems for reducing traffic accidents. In this paper, we extend our peak-finding based lane detection algorithm and the spatiotemporal based dual warning mechanisms to an integrated H/S co-design system. The proposed digital hardware scheme was built by extracting the regular high-computation modules from the entire LDWS algorithm. An innovative buffering circuit design, the Vertical Shifter (VS), is presented to speed up the in-circuit communication time. The whole system has been developed in an FPGA platform embedded with Nios II processor. Generally, our integrated H/S LDWS is capable of more flexible control capability associated with novel hardware accelerator in a system on a programmable chip (SOPC).

Original languageEnglish
Title of host publication2012 IEEE International Conference on Vehicular Electronics and Safety, ICVES 2012
Pages201-204
Number of pages4
DOIs
StatePublished - 2012
Externally publishedYes
Event2012 IEEE International Conference on Vehicular Electronics and Safety, ICVES 2012 - Istanbul, Turkey
Duration: 24 07 201227 07 2012

Publication series

Name2012 IEEE International Conference on Vehicular Electronics and Safety, ICVES 2012

Conference

Conference2012 IEEE International Conference on Vehicular Electronics and Safety, ICVES 2012
Country/TerritoryTurkey
CityIstanbul
Period24/07/1227/07/12

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