A lane departure warning system with FPGA modular design

The visual based Lane Departure Warning System (LDWS) is one of the emerging systems for reducing traffic accidents. In this paper, we extend our peak-finding based lane detection algorithm and the spatiotemporal based dual warning mechanisms to an integrated H/S co-design system. The proposed digital hardware scheme was built by extracting the regular high-computation modules from the entire LDWS algorithm. An innovative buffering circuit design, the Vertical Shifter (VS), is presented to speed up the in-circuit communication time. The whole system has been developed in an FPGA platform embedded with Nios II processor. Generally, our integrated H/S LDWS is capable of more flexible control capability associated with novel hardware accelerator in a system on a programmable chip (SOPC).