A lock-in enhanced phase-locked loop with high speed phase frequency detector

Hwang Cherng Chow*, Nan Liang Yeh

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this paper, both a high speed phase frequency detector and enhanced lock-in design are proposed for PLL design. The proposed phase frequency detector is simple in its structure and has no glitch output as well as better phase characteristics. Based on simulation results, the proposed phase frequency detector shows satisfactory circuit performance with higher operation frequency up to 3.5 GHz, lower phase jitter and smaller circuit complexity. Furthermore, we present a simple enhanced lock-in system for phase-locked loop. The proposed mechanism can reduce the lock-time effectively by using the reference clock signal only. Besides, the whole enhanced lock-in circuit performs its operation in one reference clock cycle.

Original languageEnglish
Title of host publicationProceedings of 2005 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2005
Pages401-404
Number of pages4
StatePublished - 2005
Event2005 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2005 - Hong Kong, China
Duration: 13 12 200516 12 2005

Publication series

NameProceedings of 2005 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2005
Volume2005

Conference

Conference2005 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2005
Country/TerritoryChina
CityHong Kong
Period13/12/0516/12/05

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