A lock-in enhanced phase-locked loop with high speed phase frequency detector

In this paper, both a high speed phase frequency detector and enhanced lock-in design are proposed for PLL design. The proposed phase frequency detector is simple in its structure and has no glitch output as well as better phase characteristics. Based on simulation results, the proposed phase frequency detector shows satisfactory circuit performance with higher operation frequency up to 3.5 GHz, lower phase jitter and smaller circuit complexity. Furthermore, we present a simple enhanced lock-in system for phase-locked loop. The proposed mechanism can reduce the lock-time effectively by using the reference clock signal only. Besides, the whole enhanced lock-in circuit performs its operation in one reference clock cycle.