A low-phase-noise area-efficient 3-D LC VCO in standard 0.18-um CMOS technology

Hsiao Chin Chen*, Tao Wang, Shey Shi Lu, Guo Wei Huang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

A miniaturized (0.224 mm2) 4.5-5.0 GHz 3-D LC VCO possessing area-efficient metal-6 on-chip inductors is implemented in 0.18 um 1P6M CMOS technology. With inductors directly above the other devices, this VCO shows a measured phase noise of -124.6 dBc / Hz at 1 MHz offset from the 4.9 GHz carrier while dissipating 24 mW. The figure-of-merit (-184.7 dBc/Hz) achieved is better than most of the previous state-of-art results of the CMOS LC VCOs while occupying only half the die area.

Original languageEnglish
Title of host publication2006 IEEE Mediterranean Electrotechnical Conference, MELECON 2006 - Circuits and Systems for Signal Processing, lnformation and Communication Technologies, and Power Sources and Systems
Pages202-205
Number of pages4
StatePublished - 2006
Externally publishedYes
Event2006 IEEE Mediterranean Electrotechnical Conference, MELECON 2006 - Benalmadena, Malaga, Spain
Duration: 16 05 200619 05 2006

Publication series

NameProceedings of the Mediterranean Electrotechnical Conference - MELECON
Volume2006

Conference

Conference2006 IEEE Mediterranean Electrotechnical Conference, MELECON 2006
Country/TerritorySpain
CityBenalmadena, Malaga
Period16/05/0619/05/06

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