A low-power area-efficient SRAM with enhanced read stability in 0.18-μm CMOS

Engineering

• Stability 100%
• Random Access Memory 100%
• Cycles 33%
• Networks (Circuits) 33%
• Architecture 33%
• Performance 16%
• Power Supply 16%
• Efficiency 16%
• Nodes 16%
• Bit Line 16%
• Electric Power Utilization 16%
• Prototype 16%
• Cell Area 16%
• Inverter 16%
• Similarities 16%
• Direct Connection 16%
• Aspect Ratio 16%
• Noise Margin 16%

Computer Science

• Static Random Access Memory 100%
• Power Consumption 16%
• Power Efficiency 16%
• Read Operation 16%
• Power Efficient 16%
• Memory Architecture 16%
• Efficient Operation 16%
• Direct Connection 16%
• Conventional Architecture 16%
• Noise Margin 16%