Abstract
This paper describes an memory efficient array architecture with data-rings for the 3-step hierarchical search block-matching algorithm. With the efficient data-rings and memory organization, the regular raster-scanned data flow and comparator-tree structure can be used to simplify control scheme and reduce latency, respectively. The results demonstrate that the array architecture with memory efficient scheme requires a smaller memory and low input ports.
| Original language | English |
|---|---|
| Pages (from-to) | 166-167 |
| Number of pages | 2 |
| Journal | Digest of Technical Papers - IEEE International Conference on Consumer Electronics |
| State | Published - 2001 |
| Externally published | Yes |
| Event | 2001 Digest of Technical Papers -International Conference on Consumer Electronics - Los Angeles, CA, United States Duration: 19 06 2001 → 21 06 2001 |