A multi-stage fault-tolerant multiplier with Triple Module Redundancy (TMR) technique

Ping Yeh Yin, Yuan Ho Chen, Chih Wen Lu, Shian Shing Shyu, Chung Lin Lee, Ting Chia Ou, Yo Sheng Lin

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

10 Scopus citations

Abstract

This study proposes a multistage fault-tolerant (MSFT) scheme for fixed-width array multipliers. The proposed MSFT multipliers divide the array multiplier into multiple stages, and implement a single processing element (PE) by regarding multiple computation cycles to achieve a low area design. To tolerate the fault that occurs in the integrated circuit, three redundancy replicas of PE (TMR-PE) architecture are proposed. Thus, the MSFT multiplier employs the TMR-PEs to achieve a low-cost fault-tolerant design. The TMR-PEs are designed by using compressors with multiple operands, such as 4-2 compressors or other compressors with more operands, to reduce computation cycles and speed up the execution time. Because of implementation with a 0:18-um CMOS process, the long word-length MSFT multiplier saves a significant amount of the circuit area. The proposed 64 x 64 MSFT multiplier has only 13% of the circuit area and 3% of the delay overhead of the original multiplier. Based on the measurements of the area-delay product (AT) metric, the value of the 64 x 64 MSFT multiplier is only 0:21 fold of the value of the original multiplier. Consequently, the proposed MSFT multipliers achieve a low-cost fault-tolerant design.

Original languageEnglish
Title of host publicationProceedings - 4th International Conference on Intelligent Systems, Modelling and Simulation, ISMS 2013
Pages636-641
Number of pages6
DOIs
StatePublished - 2013
Externally publishedYes
Event4th International Conference on Intelligent Systems, Modelling and Simulation, ISMS 2013 - Bangkok, Thailand
Duration: 29 01 201331 01 2013

Publication series

NameProceedings - International Conference on Intelligent Systems, Modelling and Simulation, ISMS
ISSN (Print)2166-0662
ISSN (Electronic)2166-0670

Conference

Conference4th International Conference on Intelligent Systems, Modelling and Simulation, ISMS 2013
Country/TerritoryThailand
CityBangkok
Period29/01/1331/01/13

Keywords

  • Fixed-width array multiplier
  • Multistage faulttolerant (MSFT) multiplier
  • Triple module redundancy

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