A multi-stage fault-tolerant multiplier with Triple Module Redundancy (TMR) technique

This study proposes a multistage fault-tolerant (MSFT) scheme for fixed-width array multipliers. The proposed MSFT multipliers divide the array multiplier into multiple stages, and implement a single processing element (PE) by regarding multiple computation cycles to achieve a low area design. To tolerate the fault that occurs in the integrated circuit, three redundancy replicas of PE (TMR-PE) architecture are proposed. Thus, the MSFT multiplier employs the TMR-PEs to achieve a low-cost fault-tolerant design. The TMR-PEs are designed by using compressors with multiple operands, such as 4-2 compressors or other compressors with more operands, to reduce computation cycles and speed up the execution time. Because of implementation with a 0:18-um CMOS process, the long word-length MSFT multiplier saves a significant amount of the circuit area. The proposed 64 x 64 MSFT multiplier has only 13% of the circuit area and 3% of the delay overhead of the original multiplier. Based on the measurements of the area-delay product (AT) metric, the value of the 64 x 64 MSFT multiplier is only 0:21 fold of the value of the original multiplier. Consequently, the proposed MSFT multipliers achieve a low-cost fault-tolerant design.