A multiplication-accumulation computation unit with optimized compressors and minimized switching activities

A low-power Multiplication-Accumulation Computation (MAC) unit using the radix-4 Booth algorithm is proposed in this work, by reducing its architectural complexity and minimizing the switching activities. However, to maintain a high performance, the critical delays and hardware complexities of MAC units are explored to derive at a MAC unit with a high performance and a low hardware complexity. In addition, a carry-save addition operation with optimized compressors is proposed to omit the use of half adders to further reduce the hardware complexity. Furthermore, the scheme to reduce the switching activity is proposed in this work to lower the power consumption of the proposed MAC unit. In performing a MAC for X×Y+Z, the effective dynamic ranges of X and Y are detected, the one with the smaller effective dynamic range is processed for Booth decoding so as to increase the probability of the partial products being zero, and thus the switching activity of the MAC unit is reduced. Moreover, the effective dynamic range of the result from this multiplication is also estimated and compared with the effective dynamic range of the datum, Z. The larger effective dynamic range of the two data is considered as the effective word length for an addition operation. Pipelined latches are used to make the non-effective operation maintaining the status of the previous operation so to reduce the switching activities from the addition performed in MAC. After the addition operation, sign extension is performed on the result from the effective sign bit copied to non-effective bits to derive at a correct output datum. When comparing to the conventional MAC units, the proposed MAC unit is able to reduce 21.09% to 43.74% of power consumption. Additionally, the proposed MAC unit outperforms the conventional ones in comparing the product of critical delay, area, and power consumption.