A new architecture of median filters with linear hardware complexity

C. J. Tsai*, E. H. Lu, C. H. Chen, J. Y. Lee, I. C. Jou

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

3 Scopus citations

Abstract

A novel algorithm of median filters for VLSI implementation is proposed. The architecture based on this algorithm has modular, regular, locally connected and expansible features. The throughput of the filter is independent of the window size and the hardware complexity is O(WN), where W is the window size and N is the bit number per pixel. The algorithm is based on storing an ordered list of the input data and updating the list as a new datum arrives. The new input datum is compared, in parallel, with all the values in the ordered list to find the position where it can be inserted into the list. This approach is efficient in hardware and suitable for fast software implementation. An application to 2-D image processing is discussed.

Original languageEnglish
Pages (from-to)101-103
Number of pages3
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume1
StatePublished - 1991
Externally publishedYes
Event1991 IEEE International Symposium on Circuits and Systems Part 1 (of 5) - Singapore, Singapore
Duration: 11 06 199114 06 1991

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