A new CMOS image sensor for low voltage and low power applications

In this paper a new rail-to-rail pixel readout architecture is proposed to enhance the performance of CMOS image sensor for both low voltage and low power applications. Due to this new readout circuit, the large enough input voltage swing under a low supply voltage is achieved and is then guaranteed for correct successive signal processing. As a consequence, the ability of working under a lower voltage using the same process is greatly improved. The layout size of each pixel is 17um×11.55um. The design of a 64×64 bits CMOS image sensor circuit has been completed. The proposed CMOS image sensor can extend its operating voltage from 3.3V even down to 1.8V for a 0.35um process. The accepted input voltage range is a full swing for 3.3V VDD while for 1.8V VDD the voltage level of the input ranges from 0.2V to 1.8V. The allowed output voltage swings for improved dynamic range are 0.2V∼2.8V and 0.4V∼1.6V for 3.3V and 1.8V VDD, respectively. The total power dissipation is 0.528mW at 3.3V supply and down to 0.102mW at 1.8V.