A new noise-tolerant dynamic circuit design with enhanced PDP performance under low SNR environment

You Gang Chen; I. Chyn Wey; An Yeu Wu

doi:10.1109/ASSCC.2006.357909

A new noise-tolerant dynamic circuit design with enhanced PDP performance under low SNR environment

You Gang Chen^*
, I. Chyn Wey
, An Yeu Wu

^*Corresponding author for this work

National Taiwan University

Research output: Contribution to conference › Conference Paper › peer-review

1 Scopus citations

Abstract

As the supply voltage is scaling down, both SNR and the circuit noise immunity are reduced. In this paper, we develop a new isolated noise-tolerant technique to prevent the dynamic circuit from the noise interference. As compared with the state of the art design, the noise immunity can be enhanced by 1.5X. For enhancing the noise-tolerance, we can save 81% power delay product (PDP) in severe low SNR environment. Moreover, the proposed circuit can achieve 81% and 39% energy saving as compared with the conventional domino circuit and twin-transistor design, respectively.

Original language	English
Pages	295-298
Number of pages	4
DOIs	https://doi.org/10.1109/ASSCC.2006.357909
State	Published - 2006
Externally published	Yes
Event	2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 - Hangzhou, China Duration: 13 11 2006 → 15 11 2006

Conference

Conference	2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006
Country/Territory	China
City	Hangzhou
Period	13/11/06 → 15/11/06

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10.1109/ASSCC.2006.357909

Cite this

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title = "A new noise-tolerant dynamic circuit design with enhanced PDP performance under low SNR environment",

abstract = "As the supply voltage is scaling down, both SNR and the circuit noise immunity are reduced. In this paper, we develop a new isolated noise-tolerant technique to prevent the dynamic circuit from the noise interference. As compared with the state of the art design, the noise immunity can be enhanced by 1.5X. For enhancing the noise-tolerance, we can save 81\% power delay product (PDP) in severe low SNR environment. Moreover, the proposed circuit can achieve 81\% and 39\% energy saving as compared with the conventional domino circuit and twin-transistor design, respectively.",

author = "Chen, \{You Gang\} and Wey, \{I. Chyn\} and Wu, \{An Yeu\}",

year = "2006",

doi = "10.1109/ASSCC.2006.357909",

language = "英语",

pages = "295--298",

note = "2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 ; Conference date: 13-11-2006 Through 15-11-2006",

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AU - Chen, You Gang

AU - Wey, I. Chyn

AU - Wu, An Yeu

PY - 2006

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N2 - As the supply voltage is scaling down, both SNR and the circuit noise immunity are reduced. In this paper, we develop a new isolated noise-tolerant technique to prevent the dynamic circuit from the noise interference. As compared with the state of the art design, the noise immunity can be enhanced by 1.5X. For enhancing the noise-tolerance, we can save 81% power delay product (PDP) in severe low SNR environment. Moreover, the proposed circuit can achieve 81% and 39% energy saving as compared with the conventional domino circuit and twin-transistor design, respectively.

AB - As the supply voltage is scaling down, both SNR and the circuit noise immunity are reduced. In this paper, we develop a new isolated noise-tolerant technique to prevent the dynamic circuit from the noise interference. As compared with the state of the art design, the noise immunity can be enhanced by 1.5X. For enhancing the noise-tolerance, we can save 81% power delay product (PDP) in severe low SNR environment. Moreover, the proposed circuit can achieve 81% and 39% energy saving as compared with the conventional domino circuit and twin-transistor design, respectively.

UR - https://www.scopus.com/pages/publications/34250829744

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DO - 10.1109/ASSCC.2006.357909

M3 - 论文

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T2 - 2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006

Y2 - 13 November 2006 through 15 November 2006

ER -

A new noise-tolerant dynamic circuit design with enhanced PDP performance under low SNR environment

Abstract

Conference

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