A new rail-to-rail readout circuit of CMOS image sensor for low power applications

Hwang Cherng Chow; J. B. Hsiao

doi:10.1109/MWSCAS.2005.1594277

A new rail-to-rail readout circuit of CMOS image sensor for low power applications

Hwang Cherng Chow^*, J. B. Hsiao

^*Corresponding author for this work

Department of Electronic Engineering

Chang Gung University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

In order to enhance the performance of CMOS image sensor under lower supply voltage, a new rail-to-rail pixel readout architecture is proposed in this paper. Due to the new readout circuit, the enough input voltage swing under low supply voltage is achieved and guaranteed for correct successive signal processing. As a consequence, the ability of working under lower voltage using the same process is greatly improved. The layout size of each pixel is 17um×11.55um. The design of a 64×64 bits CMOS image sensor circuit has been completed. The proposed CMOS image sensor can extend its operating voltage from 3.3V even down to 1.8V for a 0.35um process. The total power dissipation is 0.528mW at 3.3V supply and down to 0.102mW at 1.8V

Original language	English
Title of host publication	2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005
Pages	1019-1022
Number of pages	4
DOIs	https://doi.org/10.1109/MWSCAS.2005.1594277
State	Published - 2005
Event	2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005 - Cincinnati, OH, United States Duration: 07 08 2005 → 10 08 2005

Publication series

Name	Midwest Symposium on Circuits and Systems
Volume	2005
ISSN (Print)	1548-3746

Conference

Conference	2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005
Country/Territory	United States
City	Cincinnati, OH
Period	07/08/05 → 10/08/05

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10.1109/MWSCAS.2005.1594277

Cite this

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title = "A new rail-to-rail readout circuit of CMOS image sensor for low power applications",

abstract = "In order to enhance the performance of CMOS image sensor under lower supply voltage, a new rail-to-rail pixel readout architecture is proposed in this paper. Due to the new readout circuit, the enough input voltage swing under low supply voltage is achieved and guaranteed for correct successive signal processing. As a consequence, the ability of working under lower voltage using the same process is greatly improved. The layout size of each pixel is 17um×11.55um. The design of a 64×64 bits CMOS image sensor circuit has been completed. The proposed CMOS image sensor can extend its operating voltage from 3.3V even down to 1.8V for a 0.35um process. The total power dissipation is 0.528mW at 3.3V supply and down to 0.102mW at 1.8V",

author = "Chow, {Hwang Cherng} and Hsiao, {J. B.}",

year = "2005",

doi = "10.1109/MWSCAS.2005.1594277",

language = "英语",

isbn = "0780391977",

series = "Midwest Symposium on Circuits and Systems",

pages = "1019--1022",

booktitle = "2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005",

note = "2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005 ; Conference date: 07-08-2005 Through 10-08-2005",

}

Chow, HC & Hsiao, JB 2005, A new rail-to-rail readout circuit of CMOS image sensor for low power applications. in 2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005., 1594277, Midwest Symposium on Circuits and Systems, vol. 2005, pp. 1019-1022, 2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005, Cincinnati, OH, United States, 07/08/05. https://doi.org/10.1109/MWSCAS.2005.1594277

A new rail-to-rail readout circuit of CMOS image sensor for low power applications. / Chow, Hwang Cherng; Hsiao, J. B.
2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005. 2005. p. 1019-1022 1594277 (Midwest Symposium on Circuits and Systems; Vol. 2005).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - In order to enhance the performance of CMOS image sensor under lower supply voltage, a new rail-to-rail pixel readout architecture is proposed in this paper. Due to the new readout circuit, the enough input voltage swing under low supply voltage is achieved and guaranteed for correct successive signal processing. As a consequence, the ability of working under lower voltage using the same process is greatly improved. The layout size of each pixel is 17um×11.55um. The design of a 64×64 bits CMOS image sensor circuit has been completed. The proposed CMOS image sensor can extend its operating voltage from 3.3V even down to 1.8V for a 0.35um process. The total power dissipation is 0.528mW at 3.3V supply and down to 0.102mW at 1.8V

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Y2 - 7 August 2005 through 10 August 2005

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A new rail-to-rail readout circuit of CMOS image sensor for low power applications

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